Semiconductor devices

• US 10,446,774 B2
• Filed: 01/13/2018
• Issued: 10/15/2019
• Est. Priority Date: 06/20/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Yi-Koan, Moon, Kwang-Jin, Lee, Nae-In, Lee, Ho-Jin
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US15/870,922
• Publication Number:
  US 20180366671A1
• Time in Patent Office: 640 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/05007 comprising a core and a coating
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05564 Only on the bonding interface of the bonding area
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 : the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 : the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05576 : being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/05578 : being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05693 : with a principal constituent of the material being a solid not provided for in groups H01L2224/056 - H01L2224/05691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/0603 : Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 : Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/08057 : in side view
• CPC Class Codes: H01L 2224/0807 : of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/08147 : the bonding area connecting to a bonding area disposed in a recess of the surface of the body
• CPC Class Codes: H01L 2224/09517 : including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/8034 : Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/53223 : Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53276 : containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/538 : the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H10K 30/821 : comprising carbon nanotubes
• CPC Class Codes: H10K 85/221 : Carbon nanotubes
• CPC Class Codes: Y02E 10/549 : Organic PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Claims

1. A semiconductor device, comprising:

a first conductive pattern contained at an upper portion of a first insulating interlayer on a first substrate;

a first plurality of carbon nanotubes (CNTs) extending in a vertical direction relative to an upper surface of the first substrate, at least a portion of a sidewall of each of the first plurality of CNTs being covered by the first conductive pattern;

a second conductive pattern contained at a lower portion of a second insulating interlayer beneath a second substrate, a lower surface of the second insulating interlayer contacting an upper surface of the first insulating interlayer; and

a second plurality of CNTs extending in the vertical direction, at least a portion of a sidewall of each of the second plurality of CNTs being covered by the second conductive pattern,

wherein the first and second conductive patterns face each other in the vertical direction, wherein the first plurality of CNTs and the second plurality of CNTs are opposite to each other in the vertical direction, and wherein at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other; and

wherein a top surface of the at least one of the first plurality of CNTs and a bottom surface of the at least one of the second plurality of CNTs contact each other.

2. The semiconductor device of claim 1, wherein top surfaces of the first plurality of CNTs are substantially coplanar with a top surface of the first insulating interlayer, and bottom surfaces of the second plurality of CNTs are substantially coplanar with a bottom surface of the second insulating interlayer.

3. The semiconductor device of claim 1, wherein an upper sidewall of the at least one of the first plurality of CNTs and a lower sidewall of the at least one of the second plurality of CNTs contact each other.

4. The semiconductor device of claim 3, wherein heights of top surfaces of the first plurality of CNTs are higher than that of a top surface of the first insulating interlayer, and heights of bottom surfaces of the second plurality of CNTs are lower than that of a bottom surface of the second insulating interlayer.

5. The semiconductor device of claim 1, wherein a top surface of the first conductive pattern and a bottom surface of the second conductive pattern contact each other.

6. The semiconductor device of claim 1, wherein a first air gap is present between the first and second conductive patterns.

7. The semiconductor device of claim 1, further comprising:

a first barrier pattern covering a lower surface and a sidewall of the first conductive pattern; and

a second barrier pattern covering an upper surface and a sidewall of the second conductive pattern.

8. The semiconductor device of claim 7, wherein bottom surfaces of the first plurality of CNTs contact a surface of the first barrier pattern, and top surfaces of the second plurality of CNTs contact a surface of the second barrier pattern.

9. The semiconductor device of claim 5, further comprising:

a first insulation pattern contained at an upper portion of the first insulating interlayer;

a third plurality of CNTs extending in the vertical direction, at least a portion of a sidewall of each of the third plurality of CNTs being covered by the first insulation pattern;

a second insulation pattern contained at a lower portion of the second insulating interlayer; and

a fourth plurality of CNTs extending in the vertical direction, at least a portion of a sidewall of each of the fourth plurality of CNTs being covered by the second insulation pattern,

wherein the first and second insulation patterns face each other in the vertical direction, and at least one of the third plurality of CNTs and at least one of the fourth plurality of CNTs contact each other.

10. The semiconductor device of claim 9, wherein a top surface of the first insulation pattern and a bottom surface of the second insulation pattern contact each other.

11. The semiconductor device of claim 9, wherein a second air gap is present between the first and second insulation patterns.

12. The semiconductor device of claim 1, wherein the first and second insulating interlayers include at least substantially the same material, and the first and second conductive patterns includes at least substantially the same material.

13. A semiconductor device, comprising:

a first conductive pattern contained at an upper portion of a first insulating interlayer on a first substrate;

a first plurality of carbon nanotubes (CNTs) on a first recess on an upper surface of the first conductive pattern, each of the first plurality of CNTs extending in a vertical direction relative to an upper surface of the first substrate;

a second conductive pattern contained at a lower portion of a second insulating interlayer beneath a second substrate, a lower surface of the second insulating interlayer contacting an upper surface of the first insulating interlayer; and

a second plurality of CNTs beneath a second recess beneath a lower surface of the second conductive pattern, each of the second plurality of CNTs extending in the vertical direction,

wherein the first and second conductive patterns face each other in the vertical direction, wherein a top surface of at least one of the first plurality of CNTs is spaced apart from the second conductive pattern and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

14. The semiconductor device of claim 13, wherein a top surface of the at least one of the first plurality of CNTs and a bottom surface of the at least one of the second plurality of CNTs contact each other.

15. The semiconductor device of claim 13, wherein an upper sidewall of the at least one of the first plurality of CNTs and a lower sidewall of the at least one of the second plurality of CNTs contact each other.

16. The semiconductor device of claim 13, further comprising:

a first insulation pattern contained at an upper portion of the first insulating interlayer;

a third plurality of CNTs extending in the vertical direction, at least a portion of a sidewall of each of the third plurality of CNTs being covered by the first insulation pattern;

a second insulation pattern contained at a lower portion of the second insulating interlayer; and

a fourth plurality of CNTs extending in the vertical direction, at least a portion of a sidewall of each of the fourth plurality of CNTs being covered by the second insulation pattern,

wherein the first and second insulation patterns face each other in the vertical direction, and at least one of the third plurality of CNTs and at least one of the fourth plurality of CNTs contact each other.

17. A semiconductor device, comprising:

a first conductive pattern;

a first plurality of carbon nanotubes (CNTs) extending through the first conductive pattern in a vertical direction, each of the first plurality of CNTs protruding from an upper surface of the first conductive pattern;

a second conductive pattern; and

a second plurality of CNTs extending through the second conductive pattern in the vertical direction, each of the second plurality of CNTs protruding from a lower surface of the second conductive pattern,

wherein an upper portion of at least one of the first plurality of CNTs and a lower portion of at least one of the second plurality of CNTs contact each other.

18. The semiconductor device of claim 17, wherein an upper sidewall of the at least one of the first plurality of CNTs and a lower sidewall of the at least one of the second plurality of CNTs contact each other.

19. The semiconductor device of claim 17, wherein an air gap is present between the first and second conductive patterns.