Hybrid differential amplifier and method thereof

• US 10,447,218 B1
• Filed: 07/16/2018
• Issued: 10/15/2019
• Est. Priority Date: 07/16/2018
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Xie, Juan, Leong, Poh Boon, Lin, Chia-Liang (Leon)
• Primary Examiner(s): Choe, Henry
• Application Number:
  US16/035,897
• Time in Patent Office: 456 Days
• Field of Search: 330253, 330261
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2203/45216 A cross coupling circuit being added at the output terminals of the amplifying transistors of a differential amplifier
• CPC Class Codes: H03F 2203/45332 the AAC comprising one or more capacitors as feedback circuit elements
• CPC Class Codes: H03F 2203/45662 the LC comprising inductive coupled loading elements
• CPC Class Codes: H03F 2203/45714 the LC comprising a coil as shunt
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages

Abstract

An apparatus includes a first common-source amplifier having a first PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first voltage and output a first current; a second common-source amplifier having a first NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second voltage and output a second current, wherein the first common-source amplifier and the second common-source amplifier share a common source node, and an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage; a first common-gate amplifier having a second PMOS transistor configured to receive the first current and output a third current; a second common-gate amplifier having a second NMOS transistor configured to receive the second current and output a fourth current; and a load configured to terminate the third current and the fourth current.

Claims

1. An apparatus comprising:

a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first voltage and output a first current;

a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second voltage and output a second current, wherein the first common-source amplifier and the second common-source amplifier share a common source node, and an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage;

a first common-gate amplifier comprising a second PMOS transistor configured to receive the first current and output a third current;

a second common-gate amplifier comprising a second NMOS transistor configured to receive the second current and output a fourth current; and

a load configured to terminate the third current and the fourth current,

wherein the load comprises a first inductor inserted between the drain of the second PMOS transistor and a ground node and the first inductor is directly connected to the ground node, and a second inductor inserted between the drain of the second NMOS transistor and a power node and the second inductor is directly connected to the power node.

2. The apparatus of claim 1 wherein the load further comprises a tuning capacitor configured to tune an impedance of the load.

3. The apparatus of claim 2, wherein:

the gate of the second PMOS transistor is DC (direct-current) coupled to a first bias voltage;

the gate of the second NMOS transistor is DC coupled to a second bias voltage;

the source of the second NMOS transistor is AC coupled to the gate of the second PMOS transistor; and

the source of the second PMOS transistor is AC coupled to the gate of the second NMOS transistor.

4. The apparatus of claim 2, wherein:

the gate of the second PMOS transistor is DC (direct-current) coupled to a first bias voltage;

the gate of the second NMOS transistor is DC coupled to a second bias voltage;

the drain of the second NMOS transistor is AC coupled to the gate of the second PMOS transistor; and

the drain of the second PMOS transistor is AC coupled to the gate of the second NMOS transistor.

5. An apparatus comprising:

a first hybrid differential amplifier configured to receive a first input signal and a second input signal and output a first output signal and a second output signal using a first cascode amplifier and a second cascode amplifier, respectively; and

a second hybrid differential amplifier configured to receive a third input signal and a fourth input signal and output a third output signal and a fourth output signal using a third cascode amplifier and a fourth cascode amplifier, respectively;

wherein;

the first cascode amplifier and the third cascode amplifier are based on using PMOS (p-channel metal oxide semiconductor) transistors, the second cascode amplifier and the fourth cascode amplifier are based on using NMOS (n-channel metal oxide semiconductor) transistors, a DC (direct current) component of the first input signal is the same as a DC component of the third input signal, a DC component of the second input signal is the same as a DC component of the fourth input signal, an AC (alternating current) component of the first input signal is the same as an AC component of the fourth input signal, an AC component of the second input signal is the same as an AC component of the third input signal, and the AC component of the second input signal is an inversion of the AC component of the first input signal.

6. The apparatus of claim 5 further comprising:

a first load comprising a first inductor and a second inductor configured to provide a termination for the first output signal and the second output signal, respectively, and a second load comprising a third inductor and a fourth inductor configured to provide a termination for the third output signal and the fourth output signal, respectively.

7. The apparatus of claim 6 further comprising a power combining network comprising a fifth inductor, a sixth inductor, a seventh inductor, and an eighth inductor configured to have an inductive coupling with the first inductor, the second inductor, the third inductor, and the fourth inductor, respectively.

8. The apparatus of claim 7, wherein the fifth inductor, the sixth inductor, the seventh inductor, and the eighth inductor are connected in a way such their respective voltages are effectively summed.

9. The apparatus of claim 7, wherein the fifth inductor, the sixth inductor, the seventh inductor, and the eighth inductor are connected in a way such their respective currents are effectively summed.

10. A method comprising:

receiving a first voltage and a second voltage, wherein an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage;

converting the first voltage into a first current using a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor;

converting the second voltage into a second current using a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common source node;

relaying the first current into a third current using a first common-gate amplifier comprising a second PMOS transistor;

relaying the second current into a fourth current using a second common-gate amplifier comprising a second NMOS transistor; and

terminating the third current and the fourth current with a load,

wherein the load comprises a first inductor inserted between the drain of the second PMOS transistor and a ground node and the first inductor is directly connected to the ground node, and a second inductor inserted between the drain of the second NMOS transistor and a power node and the second inductor is directly connected to the power node.

11. The method of claim 10, wherein the load further comprises a tuning capacitor configured to tune an impedance of the load.

12. The method of claim 11, wherein:

the gate of the second PMOS transistor is DC (direct-current) coupled to a first bias voltage;

the gate of the second NMOS transistor is DC coupled to a second bias voltage;

the source of the second NMOS transistor is AC coupled to the gate of the second PMOS transistor; and

the source of the second PMOS transistor is AC coupled to the gate of the second NMOS transistor.

13. The method of claim 11, wherein:

the gate of the second PMOS transistor is DC (direct-current) coupled to a first bias voltage;

the gate of the second NMOS transistor is DC coupled to a second bias voltage;

the drain of the second NMOS transistor is AC coupled to the gate of the second PMOS transistor; and

the drain of the second PMOS transistor is AC coupled to the gate of the second NMOS transistor.