Three dimensional inductor-capacitor apparatus and method of fabricating

• US 10,447,226 B2
• Filed: 12/21/2017
• Issued: 10/15/2019
• Est. Priority Date: 12/21/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Liu, Yu-Chun, Ravindran, Arjun
• Primary Examiner(s): Patel, Rakesh B
• Application Number:
  US15/851,312
• Publication Number:
  US 20190200454A1
• Time in Patent Office: 663 Days
• Field of Search: 333175, 333185
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/0026 Multilayer LC-filter
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H03H 2001/0085 Multilayer, e.g. LTCC, HTCC, green sheets
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H05K 1/0284 Details of three-dimensional rigid printed circuit boards H05K1/119 takes precedence; shaping of the substrate H05K3/0014
• CPC Class Codes: H05K 1/119 Details of rigid insulating substrates therefor, e.g. three-dimensional details H05K1/117 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/165 incorporating printed inductors

Abstract

Some aspects pertain to an apparatus that includes a plurality of stacked metal layers configured in a spiral shape. The plurality of stacked metal layers include a first metal layer including a first inductor, a second metal layer including a plurality of first pads and a plurality of second pads, a third metal layer including a plurality of third pads and a plurality of fourth pads, a fourth metal layer including a second inductor, a plurality of first vias configured to couple the first metal layer to the second metal layer, a plurality of second vias configured to couple the second metal layer to the third metal layer, a plurality of third vias configured to couple the third metal layer to the fourth metal layer; and a dielectric layer at least partially surrounding the apparatus.

Claims

1. An apparatus comprising:

a plurality of stacked metal layers, including;

a first metal layer including a first inductor, the first inductor configured in a spiral shape;

a second metal layer including a plurality of first pads and a plurality of second pads;

a third metal layer including a plurality of third pads and a plurality of fourth pads;

a fourth metal layer including a second inductor, the second inductor configured in a spiral shape;

a plurality of first vias configured to couple the first metal layer to the second metal layer;

a plurality of second vias configured to couple the second metal layer to the third metal layer;

a plurality of third vias configured to couple the third metal layer to the fourth metal layer;

a dielectric layer at least partially surrounding the apparatus; and

a first capacitor, wherein the first capacitor includes at least a portion of the first metal layer, and at least one of the plurality of first pads, separated by the dielectric layer.

2. The apparatus of claim 1, further comprising:

a second capacitor, wherein the second capacitor includes one of a plurality of third pads and one of the plurality of second vias, and one of a plurality of fourth pads and a second one of a plurality of second vias, separated by the dielectric layer.

3. The apparatus of claim 1, further comprising:

a second capacitor and a third capacitor, where the first capacitor, the second capacitor, and the third capacitor have an equivalent capacitance.

4. The apparatus of claim 1, wherein the plurality of first vias is offset from the plurality of third vias.

5. The apparatus of claim 1, wherein the apparatus is integrated into a device selected from the group consisting of a package substrate, an interposer, a ceramic package, an integrated circuit, and a printed circuit board.

6. The apparatus of claim 1, wherein the at least a portion of the first metal layer is at least a portion of the first inductor.

7. The apparatus of claim 1, further comprising:

a second capacitor, wherein the second capacitor includes at least a portion of the fourth metal layer, and at least one of the plurality of third pads, separated by the dielectric layer.

8. The apparatus of claim 7, further comprising wherein the at least a portion of the fourth metal layer is at least a portion of the second inductor.

9. The apparatus of claim 7, further comprising:

a third capacitor, wherein the third capacitor includes one of a plurality of third pads and one of the plurality of second vias, and one of the plurality of fourth pads and a second one of the plurality of second vias, separated by the dielectric layer.

10. The apparatus of claim 1, further comprising:

wherein the plurality of first vias couple the first inductor to the plurality of second pads; and

wherein the plurality of third vias couple the second inductor to the plurality of fourth pads.

11. The apparatus of claim 10, further comprising:

wherein the plurality of second vias couple the plurality of fourth pads to the plurality of first pads, and wherein the plurality of second vias couple the plurality of third pads to the plurality of second pads.

12. The apparatus of claim 1, wherein the first inductor and the second inductor are stacked so that the spiral shape of the first inductor and the spiral shape of the second inductor at least partially mirror each other.

13. The apparatus of claim 12, wherein the plurality of first vias, the plurality of first pads, the plurality of second pads, the plurality of second vias, the plurality of third pads, the plurality of fourth pads and the plurality of third vias are configured in the spiral shape and stacked to at least partially mirror the spiral shape of the first inductor and second inductor.

14. The apparatus of claim 1, wherein the first inductor and the second inductor are configured to provide mutual inductance.

15. The apparatus of claim 1, wherein the dielectric layer comprises a plurality of dielectric layers.

16. The apparatus of claim 1, wherein the apparatus is an LC resonant circuit.

17. The apparatus of claim 1, wherein the apparatus further comprises a device selected from the group consisting of:

a resonant circuit, a radio frequency choke, and band-pass filter.

18. A method of fabricating an apparatus comprising:

forming a plurality of stacked metal layers, including;

forming a first metal layer including forming a first inductor in a spiral shape;

forming a second metal layer including forming a plurality of first pads and a plurality of second pads;

forming a third metal layer including forming a plurality of third pads and a plurality of fourth pads;

forming a fourth metal layer including forming a second inductor in a spiral shape;

forming a plurality of first vias and coupling the first metal layer to the second metal layer;

forming a plurality of second vias and coupling the second metal layer to the third metal layer;

forming a plurality of third vias and coupling the third metal layer to the fourth metal layer;

forming a dielectric layer at least partially surrounding the apparatus; and

forming a first capacitor, wherein the first capacitor includes at least a portion of the first metal layer, and at least one of the plurality of first pads, separated by the dielectric layer.

19. The method of claim 18, further comprising:

stacking the first inductor and the second inductor so that the spiral shape of the first inductor and the spiral shape of the second inductor at least partially mirror each other.

20. The method of claim 19, further including forming the plurality of first vias, the plurality of first pads, the plurality of second pads, the plurality of second vias, the plurality of third pads, the plurality of fourth pads and the plurality of third vias in the spiral shape and stacking them to at least partially mirror the spiral shape of the first inductor and second inductor.

21. The method of claim 18 further comprising:

forming a second capacitor, wherein the second capacitor is formed of one of a plurality of third pads and one of the plurality of second vias, and one of a plurality of fourth pads and a second one of a plurality of second vias, separated by the dielectric layer.

22. The method of claim 18, further comprising forming the plurality of first vias so they are offset from the plurality of third vias.

23. The method of claim 18, wherein forming the plurality of first vias includes coupling the first inductor to the plurality of second pads, and wherein forming the plurality of third vias includes coupling the second inductor to the plurality of fourth pads.

24. The method of claim 23, wherein forming the plurality of second vias includes coupling the plurality of fourth pads to the plurality of first pads, and wherein forming the plurality of second vias includes coupling the plurality of third pads to the plurality of second pads.

25. The method of claim 18, further comprising:

forming a second capacitor, wherein the second capacitor includes at least a portion of the fourth metal layer, and at least one of the plurality of third pads, separated by the dielectric layer.