Low voltage differential signaling circuit

• US 10,447,246 B1
• Filed: 11/06/2018
• Issued: 10/15/2019
• Est. Priority Date: 11/06/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Tripathi, Divya, Gottapu, Anil Kumar, Wadhwa, Sanjay Kumar
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/181,518
• Time in Patent Office: 343 Days
• Field of Search: None
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/356069 using additional transistors in the feedback circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.

Claims

1. A low voltage differential signaling circuit comprising:

an output driver circuit configured to provide a differential signal pair at a differential output pair based on a first signal and a second signal, the second signal a complement of the first signal;

a first peak detect circuit coupled to receive the differential signal pair and configured to provide a first feedback signal based on the differential signal pair and the first and second signals; and

a first amplifier circuit having a first input coupled to the first peak detect circuit, a second input coupled to receive a first reference voltage, and an output coupled to provide a first bias voltage to the output driver circuit.

2. The circuit of claim 1, wherein the first peak detect circuit comprises:

a first transistor having a first current electrode coupled at a first node and a control electrode coupled to receive the first signal; and

a second transistor having a first current electrode coupled to the first current electrode of the first transistor at the first node and a control electrode coupled to receive the second signal.

3. The circuit of claim 2, wherein the first peak detect circuit further comprises:

a third transistor having a first current electrode coupled to a second current electrode of the first transistor, a second current electrode coupled at the differential output pair, and a control electrode coupled to receive a first delay signal, the first delay signal a delayed version of the first signal; and

a fourth transistor having a first current electrode coupled to a second current electrode of the second transistor, a second current electrode coupled at the differential output pair, and a control electrode coupled to receive a second delay signal, the second delay signal a delayed version of the second signal.

4. The circuit of claim 3, wherein the first peak detect circuit further comprises a filter circuit, the filter circuit comprising:

a resistor having a first terminal coupled at the first node and a second terminal coupled to the first input of the first amplifier circuit; and

a capacitor having a first terminal coupled at the second terminal of the resistor and a second terminal coupled to a first voltage supply.

5. The circuit of claim 1, further comprising:

a second peak detect circuit coupled to receive the differential signal pair and configured to provide a second feedback signal based on the differential signal pair and the first and second signals; and

a second amplifier circuit having a first input coupled to the second peak detect circuit, a second input coupled to receive a second reference voltage, and an output coupled to provide a second bias voltage to the output driver circuit.

6. The circuit of claim 5, wherein the output driver circuit further comprises:

a first transistor having a first current electrode coupled at a first voltage supply and a control electrode coupled to receive the first bias voltage;

a second transistor having a first current electrode coupled at a second voltage supply and a control electrode coupled to receive the second bias voltage; and

an H-bridge circuit coupled to a second current electrode of the first transistor and a second current electrode of the second transistor, the H-bridge circuit having a first input coupled to receive the first signal, a second input coupled to receive the second signal, and the differential output pair for providing the differential signal pair.

7. The circuit of claim 6, further comprising a reference divider circuit coupled between the first voltage supply and the second voltage supply, the reference divider circuit configured to provide the first bias voltage at a first output and the second bias voltage at a second output, and wherein the first bias voltage is approximately 75% of the first voltage supply and the second bias voltage is approximately 25% of the first voltage supply.

8. The circuit of claim 6, further comprising:

a first resistor having a first terminal coupled to the output of the first amplifier circuit and the control terminal of the first transistor;

a first capacitor having a first terminal coupled to a second terminal of the first resistor and a second terminal coupled to the second current electrode of the first transistor;

a second resistor having a first terminal coupled to the output of the second amplifier circuit and the control terminal of the second transistor; and

a second capacitor having a first terminal coupled to a second terminal of the second resistor and a second terminal coupled to the second current electrode of the second transistor.

9. The circuit of claim 6, wherein the H-bridge circuit comprises:

a third transistor having a first current electrode coupled to the second current electrode of the first transistor and a control electrode coupled at the first input;

a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor at a first output of the differential output pair, a second current electrode coupled to the second current electrode of the second transistor, and a control electrode coupled to the control electrode of the third transistor at the first input;

a fifth transistor having a first current electrode coupled to the second current electrode of the first transistor and a control electrode coupled at the second input; and

a sixth transistor having a first current electrode coupled to a second current electrode of the fifth transistor at a second output of the differential output pair, a second current electrode coupled to the second current electrode of the second transistor, and a control electrode coupled to the control electrode of the fifth transistor at the second input.

10. A low voltage differential signaling circuit comprising:

a differential driver circuit configured to provide a differential signal pair in response to a first signal and a second signal, the second signal a complement of the first signal;

a first peak detect circuit coupled to receive the differential signal pair and configured to provide a first feedback signal based on the differential signal pair and the first and second signals; and

a first amplifier circuit having a first input coupled to receive the first feedback signal, a second input coupled to receive a first reference voltage, and an output coupled to provide a first bias voltage to the differential driver circuit.

11. The circuit of claim 10, wherein the first peak detect circuit comprises:

a first transistor having a first current electrode coupled at a first node and a control electrode coupled to receive the first signal;

a second transistor having a first current electrode coupled to a second current electrode of the first transistor and a control electrode coupled to receive a first delay signal;

a third transistor having a first current electrode coupled to the first current electrode of the first transistor at the first node and a control electrode coupled to receive the second signal; and

a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor and a control electrode coupled to receive a second delay signal;

wherein a second current electrode of the second transistor and a second current electrode of the fourth transistor are coupled to receive the differential signal pair.

12. The circuit of claim 11, further comprising a delay circuit configured to provide the first delay signal at a first output as a delayed version of the first signal received at a first input and to provide the second delay signal at a second output as a delayed version of the second signal received at a second input.

13. The circuit of claim 11, wherein the first peak detect circuit further comprises:

a resistor having a first terminal coupled at the first node and a second terminal coupled to the first input of the first amplifier circuit; and

a capacitor having a first terminal coupled at the second terminal of the resistor and a second terminal coupled to a first voltage supply.

14. The circuit of claim 10, further comprising:

a second peak detect circuit coupled to receive the differential signal pair and configured to provide a second feedback signal based on the differential signal pair and the first and second signals; and

a second amplifier circuit having a first input coupled to receive the second feedback signal, a second input coupled to receive a second reference voltage, and an output coupled to provide a second bias voltage to the differential driver circuit.

15. The circuit of claim 14, further comprising a resistor divider circuit coupled between a first voltage supply and a second voltage supply, the resistor divider circuit configured to provide the first bias voltage at a first output and the second bias voltage at a second output.

16. The circuit of claim 14, further comprising:

a first compensation circuit having a first terminal coupled to the output of the first amplifier circuit and a second terminal coupled to the differential driver circuit; and

a second compensation circuit having a first terminal coupled to the output of the second amplifier circuit and a second terminal coupled to the differential driver circuit.

17. A low voltage differential signaling circuit comprising:

an output driver circuit having a first input coupled to receive a first signal, a second input coupled to receive a second signal, and a differential output pair formed by a first output and a second output, the output driver circuit configured to provide a differential signal pair at the differential output pair based on the first signal and the second signal;

a first peak detect circuit coupled to the differential output pair and configured to provide a first feedback signal based on the differential signal pair and the first and second signals; and

a first amplifier circuit having a first input coupled to receive the first feedback signal, a second input coupled to receive a first reference voltage, and an output coupled to provide a first bias voltage to the output driver circuit.

18. The circuit of claim 17, wherein the first peak detect circuit comprises:

a first transistor having a first current electrode coupled at a first node and a control electrode coupled to receive the first signal;

a second transistor having a first current electrode coupled to a second current electrode of the first transistor, a second current electrode coupled to the first output, and a control electrode coupled to receive a first delay signal, the first delay signal characterized as a delayed version of the first signal;

a third transistor having a first current electrode coupled to the first current electrode of the first transistor at the first node and a control electrode coupled to receive the second signal; and

a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor, a second current electrode coupled to the second output, and a control electrode coupled to receive a second delay signal, the second delay signal characterized as a delayed version of the second signal.

19. The circuit of claim 17, further comprising:

a second peak detect circuit coupled to the differential output pair and configured to provide a second feedback signal based on the differential signal pair and the first and second signals; and

a second amplifier circuit having a first input coupled to receive the second feedback signal, a second input coupled to receive a second reference voltage, and an output coupled to provide a second bias voltage to the output driver circuit.

20. The circuit of claim 19, further comprising a reference divider circuit coupled between a first voltage supply and a second voltage supply, the reference divider circuit configured to provide the first bias voltage at a first output and the second bias voltage at a second output.