Duty cycle correction on an interval-by-interval basis

• US 10,447,247 B1
• Filed: 04/27/2018
• Issued: 10/15/2019
• Est. Priority Date: 04/27/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Tang, Tianyu, Ramachandra, Venkatesh
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/965,099
• Publication Number:
  US 20190333551A1
• Time in Patent Office: 536 Days
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.

Claims

1. A circuit comprising:

a measurement circuit configured to;

receive an input signal comprising a plurality of transitions, each transition being a rising transition or a falling transition; and

measure an average time interval duration of a pair of consecutive time intervals of the input signal, each time interval defined by a pair of consecutively occurring transitions of the input signal; and

an output circuit configured to generate an output signal comprising a time interval having a duration set to the average time interval duration.

2. The circuit of claim 1, wherein the measurement circuit comprises a detection circuit configured to:

detect a first midpoint of a first time interval of the pair of consecutive time intervals; and

detect a second midpoint of a second time interval following the first midpoint of the first time interval of the pair of consecutive time intervals in order to measure the average time interval duration.

3. The circuit of claim 1, wherein the measurement circuit comprises:

a ramp generation circuit configured to;

generate a first pair of complementary ramp signals that perform first transitions over a first ramp period corresponding to the first interval of the pair of consecutive time intervals; and

generate second pair of complementary ramp signals that perform second transitions over a second time interval of the pair of consecutive time intervals; and

a detection circuit configured to;

detect a first cross-point of the first transitions and a second cross-point of the second transitions in order to measure the average time interval duration.

4. The circuit of claim 3, wherein the measurement circuit further comprises:

a frequency division circuit configured to generate a first signal based on rising edges of the input signal and a second signal based on falling edges of the input signal;

wherein the ramp generation circuit comprises;

a push-pull circuit configured to generate one of the first pair of complementary ramp signals;

a delay chain configured to generate a plurality of delay signals based on the first signal; and

a drive strength controller configured to continuously increase a drive strength of the push-pull circuit based on a subset of delay signals of the plurality of delay signals that transition in a time window set by the first signal and the second signal.

5. The circuit of claim 4, wherein the push-pull circuit comprises a first push-pull circuit, the drive strength comprising a first drive strength, and the ramp generation circuit comprising a second push-pull circuit configured to generate the other of the first pair of complementary ramp signals,

wherein the drive strength controller is further configured to continuously increase a drive strength of the second push-pull circuit based on the subset of delay signals of the plurality of delay signals that transition in the time window.

6. The circuit of claim 4, wherein the drive strength controller comprises:

a drive strength control signal generator configured to;

receive a delay signal of the subset of delay signals transitioning in the time window; and

transition a level of a drive strength control signal in response to transitioning the delay signal in order to increase the drive strength of the push-pull circuit.

7. The circuit of claim 6, wherein the drive strength control signal generator comprises:

a first signal sub-generator configured to generate a first internal control signal to control one of a pull-up drive strength or a push-down drive strength of the push-pull circuit; and

a second signal sub-generator configured to generate a second internal control signal to control the other of the pull-up drive strength or the push-down drive strength of the push-pull circuit.

8. The circuit of claim 7, wherein the ramp generation circuit further comprises:

an XNOR gate configured perform an XNOR logic operation on the first signal and the second signal to generate an XNOR signal;

an AND gate configured to perform an AND logic operation on the first signal and the second signal to generate an AND signal,

wherein the first signal sub-generator comprises;

a dual edge flip flop configured to receive the delay signal and the XNOR signal; and

a first NAND gate configured to perform a NAND logic operation on an output of the dual-edge flip and the second signal to generate the first internal control signal, and wherein the second signal sub-generator comprises;

a second NAND gate configured to perform a NAND operation on the first signal and the delay signal; and

an OR gate configured to perform an OR operation on an output of the second NAND gate and the AND signal to generate the second internal control signal.

9. The circuit of claim 4, wherein the drive strength controller comprises a plurality of drive strength signal generators configured to output a plurality of signals to control the drive strength of the push-pull circuit, wherein each drive strength signal generator is configured to:

receive a respective one of the plurality of delay signals; and

output a respective one of the plurality of controls signals to increase the drive strength of the push-pull circuit in response to the respective one of the plurality of delay signals transitioning in the time window.

10. The circuit of claim 9, wherein over a plurality of time windows set by the first signal and the second signal, the drive strength controller is configured to change a number of the plurality of drive strength signal generators that increase the drive strength of the push-pull circuit during ramp periods corresponding to the plurality of time windows.

11. The circuit of claim 1, wherein the input circuit comprises a plurality of time intervals forming a plurality of pairs of consecutive time intervals such that two consecutive pairs comprise a common interval, and wherein the measurement circuit is further configured to measure a plurality of average time interval durations for the plurality of pairs of consecutive time intervals.

12. A circuit comprising:

a detection circuit configured to detect midpoints of a plurality of time intervals of an input signal comprising a plurality of transitions, each transition being a rising transition or a falling transition, each time interval defined by a pair of consecutively occurring transitions of the input signal, the input signal comprising a plurality of cycles, each cycle of the plurality of cycles comprising two time intervals of the plurality of time intervals; and

an output circuit configured to set durations of consecutive time intervals of an output signal according to the detected midpoints of the plurality of time intervals of the input signal.

13. The circuit of claim 12, wherein the output circuit is further configured to:

generate an intermediate signal that performs rising transitions in response to the detected midpoints; and

generate the output signal in response to the rising transitions and not the falling transitions of the intermediate signal.

14. The circuit of claim 12, wherein the plurality of time intervals comprises a plurality of consecutive time intervals, the detection circuit configured to detect midpoints of the plurality of consecutive time intervals.

15. The circuit of claim 12, wherein the detection circuit is configured to:

generate a first pair of complementary signals and a second pair of complementary signals in response to the detected midpoints of the plurality of time intervals,

wherein the first pair and the second pair of complementary signals perform respective transitions in response to alternating detected midpoints.

16. The circuit of claim 15, wherein the output circuit is configured to:

receive the first pair and the second pair of complementary signals; and

generate a set of signals, each signal of the set configured to perform respective rising and falling transitions in response to rising transitions of a different one of a plurality of combinations of two signals from the first pair and the second pair of complementary signals.

17. The circuit of claim 16, wherein the set of signals comprises a first set of signals, and wherein the output circuit is further configured to halve pulse widths of the signals of the first set to generate a second set of signals.

18. The circuit of claim 17, wherein the output circuit is further configured:

combine pulses of the second set of signals to generate a combined signal; and

generate the output signal to perform rising and falling transitions in response to rising transitions and not falling transitions of the combined signal.

19. A system comprising:

an input circuit configured to receive a pair of complementary input signals comprising a first input signal and a second input signal;

a ramp generation circuit configured to;

generate a first pair of complementary ramp signals that transition over time durations corresponding to pulse durations of pulses of the first input signal; and

generate a second pair of complementary ramp signals that transition over time durations corresponding to pulse durations of pulses of the second input signal;

a cross-point detection circuit configured to detect a plurality of consecutive cross-points of the first and second pairs of complementary ramp signals; and

an output circuit configured to set durations of consecutive intervals of an output signal in response to detection of the plurality of consecutive cross-points of the first and second pairs of complementary ramp signals.

20. The system of claim 19, further comprising:

a frequency division circuit configured to generate first and second pairs of complementary signals based on alternating rising and falling transitions of the input signal,

wherein the ramp generation circuit comprises a push-pull circuit configured to linearly increase drive strengths over the durations corresponding to the pulse durations of the pulses of the first and second input signals in order to generate the first and second pairs of complementary ramp signals.

21. A circuit comprising:

means for generating pairs of complementary ramp signals that ramp up and ramp down over ramp periods corresponding to time durations of time intervals of an input signal, the pairs of complementary ramp signals comprising;

a first pair of complementary ramp signals that ramp up and ramp down for durations corresponding to durations of a first set of the time intervals during which the input signal is at an associated high level; and

a second pair of complementary ramp signals that ramp up and ramp down for durations corresponding to durations of a second set of the time intervals during which the input signal is at an associated low level;

means for detecting cross-points of the pairs of complementary ramp signals; and

means for generating an output signal that performs rising and falling transitions in response to the detected cross-points.

22. A method comprising:

frequency dividing an input signal to generate a first set of pre-intermediate signals;

generating a second set of pre-intermediate signals that transition over ramp periods corresponding to time windows established by the first set of pre-intermediate signals;

generating a set of intermediate signals that transition in response to detected cross-points of the second set of pre-intermediate signals;

generating a first set of post-intermediate signals based on combinations of two signals of the set of intermediate signals;

halving pulse widths of pulses of the first set of post-intermediate signals to generate a second set of post-intermediate signals;

combining pulses of the second set of post-intermediate signals to generate a third post-intermediate signal; and

frequency dividing the third post-intermediate signal to generate an output signal.