Multi-stage frequency dividers and poly-phase signal generators

• US 10,447,250 B2
• Filed: 12/02/2015
• Issued: 10/15/2019
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Bagger, Reza
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US15/522,032
• Publication Number:
  US 20170324414A1
• Time in Patent Office: 1,413 Days
• Field of Search: 327115, 327117
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/425 using bistables
• CPC Class Codes: H03K 23/483 with a base which is an odd number
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 3/37 by the use, as active elements, of gas-filled tubes, e.g. astable trigger circuits H03K3/55 takes precedence
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An electronic latch circuit, a 4-phase signal generator, a multi-stage frequency divider and a poly-phase signal generator are disclosed. The electronic latch circuit comprises an output circuit comprising a first output and a second output. The electronic latch circuit further comprises an input circuit comprising a first input, a second input and a clock signal input. The electronic latch circuit is configured to change state based on the input signals'"'"' level at the inputs of the input circuit and a present state of the output circuit. The 4-phase signal generator is built with two electronic latch circuits. The multi-stage frequency dividers and poly-phase signal generators comprise a plurality of the electronic latch circuits and 4-phase signal generators.

Claims

1. A multi-stage frequency divider comprising:

a first stage comprising a 4-phase signal generator; and

a plurality N of cascaded stages, each stage comprising 2<sup>N−

1</sup> branches, wherein N=2, 3, . . . ; and

wherein each branch comprises;

an electronic latch circuit; and

a first 4-phase signal generator; and

wherein in each branch;

the first and second inputs of the electronic latch circuit is connected to a pair of the output signals at the outputs of the 4-phase signal generator in the stage preceding it; and

the first and second outputs of the electronic latch circuit is connected to the first and second clock signal inputs of the first 4-phase signal generator in the same branch; and

the clock signal input of the electronic latch circuit is connected to the first or second clock signal input of the 4-phase signal generator in the stage preceding it.

2. The multi-stage frequency divider according to claim 1, is further configured to:

receive a first clock signal with a frequency of f_CLK at the first clock signal input of the 4-phase generator in the first stage;

receive a second clock signal which is an inverse polarity of the first clock signal at the second clock signal input of the 4-phase generator in the first stage; and

generate output signals at the N^th stage with a frequency of f_CLK/2^N at the outputs of each 4-phase generator in the N^th stage, wherein N=2, 3, . . . .

3. The multi-stage frequency divider according to claim 1, wherein each branch in any one of the stages further comprises a second 4-phase signal generator, and wherein the first and second clock signal inputs of the second 4-phase signal generator are respectively connected to the second and first clock signal inputs of the first 4-phase signal generator such that the clock signals at the inputs of the first and second 4-phase signal generators are inverse in polarity with respect to each other.