Power efficient high speed latch circuits and systems

• US 10,447,251 B2
• Filed: 12/02/2015
• Issued: 10/15/2019
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Bagger, Reza
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US15/522,052
• Publication Number:
  US 20170324402A1
• Time in Patent Office: 1,413 Days
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/425 using bistables
• CPC Class Codes: H03K 23/483 with a base which is an odd number
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 3/37 by the use, as active elements, of gas-filled tubes, e.g. astable trigger circuits H03K3/55 takes precedence
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H04B 1/40 Circuits

Abstract

The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.

Claims

1. A combiner latch circuit, comprising:

an input circuit with a first input, a second input, a clock input, and an inverted clock input;

an output circuit with a first differential output and a second differential output;

wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of;

a fourth state comprising the first differential output being at logic 1 and the second differential output being at logic 0; and

a fifth state comprising the first differential output being at logic 0 and the second differential output being at logic 1; and

wherein the input circuit is further configured to;

select the fourth state when the first input is at logic 0 and the second input is at logic 1 and the clock input encounters a leading edge from logic 0 to logic 1 and the output circuit is in the fifth state; and

select the fifth state when the first input is at logic 1 and the second input is at logic 0 and the clock input encounters a leading edge from logic 0 to logic 1 and the output circuit is in the fourth state.

2. The combiner latch circuit according to claim 1, wherein the output circuit is further configured to keep its current state when the first input is at logic 1 and the second input is at logic 1 and the clock input encounters a trailing edge from logic 1 to logic 0.

3. The combiner latch circuit according to claim 1, wherein the inverted clock input is connected to the clock input, via an inverter circuit.

4. The combiner latch circuit according to claim 1, comprising:

a first and a second branch connected in parallel between a supply voltage terminal and a ground terminal, wherein each of the first branch and the second branch comprises;

a Positive Metal Oxide Semiconductor (PMOS) transistor having a gate connected to a terminal for an inverted clock signal, and a source connected to the supply voltage terminal;

a first Negative Metal Oxide Semiconductor (NMOS) transistor arranged downstream the PMOS transistor;

a second NMOS transistor arranged downstream the first NMOS transistor, and

a third NMOS transistor arranged downstream the second NMOS transistor with a source thereof connected to the ground terminal, and a gate connected to a terminal for a clock signal; and

wherein the combiner latch circuit further comprises;

a first terminal connected to the gate of the second NMOS transistor of the first branch;

a second terminal connected to a gate of the second NMOS transistor of the second branch;

a cross-coupling of the first NMOS transistors of the first branch and the second branch, wherein

a gate of the first NMOS transistor of the first branch connected to the drain of the first NMOS transistor of the second branch; and

a gate of the first NMOS transistor of the second branch connected to the drain of the first NMOS transistor of the first branch;

wherein an input circuit comprises the PMOS transistors, the second NMOS transistors, and the third NMOS transistors of the first branch and the second branch; and

wherein an output circuit comprises the cross-coupled first NMOS transistors and the differential terminals connected to a drain of the first NMOS transistor of the first branch and the second branch, respectively.

5. The combiner latch circuit according to claim 4, wherein the PMOS transistor of the first and the second branch is a single PMOS transistor, common to the first and the second branch, with a gate connected to the clock signal input and a source connected to the supply voltage terminal and the drain connected to the first branch and the second branch of the output circuit.

6. The combiner latch circuit according to claim 4, wherein the third NMOS transistor of the first and the second branch is a single NMOS transistor, common to the first and the second branch, with a gate connected to the clock signal input and a drain connected to the first branch and the second branch and the source connected to the ground terminal.

7. The combiner latch circuit according to claim 1, comprising:

a first and a second branch connected in parallel between a supply voltage terminal and a ground terminal, wherein each of the first branch and the second branch comprises;

a first Positive Metal-Oxide Semiconductor (PMOS) transistor having a gate connected to a terminal for an inverted clock signal, and a source connected to the supply voltage terminal;

a second PMOS transistor arranged downstream the first PMOS transistor;

a first Negative Metal Oxide Semiconductor (NMOS) transistor arranged downstream the second PMOS transistor, and

a second NMOS transistor arranged downstream the first NMOS transistor with a source thereof connected to the ground terminal, and a gate connected to a terminal for a clock signal; and

wherein the combiner latch circuit further comprises;

a first terminal connected to the gate of the second PMOS transistor of the first branch;

a second terminal connected to a gate of the second PMOS transistor of the second branch;

a cross-coupling of the first NMOS transistors of the first branch and the second branch, wherein

a gate of the first NMOS transistor of the first branch connected to the drain of the first NMOS transistor of the second branch; and

a gate of the first NMOS transistor of the second branch connected to the drain of the first NMOS transistor of the first branch;

wherein an input circuit comprises the first PMOS transistors, the second PMOS transistors, and the second NMOS transistors of the first branch and the second branch; and

wherein an output circuit comprises the cross-coupled first NMOS transistors and the differential terminals connected to a drain of the first NMOS transistor of the first branch and the second branch, respectively.