High performance PLL based on PVT independent stable oscillator
First Claim
Patent Images
1. A phase-locked loop comprising:
- a phase frequency detector, a charge pump, a loop filter,a first oscillator comprising inverters, configured to generate a first current,a second oscillator comprising a scaled version of the inverters of the first oscillator,a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code,a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current,wherein input current to the second oscillator is sum of the second current and the third current.
1 Assignment
0 Petitions
Accused Products
Abstract
A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.
-
Citations
20 Claims
-
1. A phase-locked loop comprising:
-
a phase frequency detector, a charge pump, a loop filter, a first oscillator comprising inverters, configured to generate a first current, a second oscillator comprising a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A method of training a PLL for generating a frequency code comprising:
-
setting the frequency code to a default value; asserting a clamp signal to tri-state a charge pump and a phase frequency detector of the PLL, comparing a reference clock and a feedback clock using a frequency calibration block, wherein the frequency calibration block comprises a comparator and a frequency code generator, updating the frequency code based on the comparison of the reference clock and the feedback clock, wherein the updation of the frequency code is performed till the difference between reference clock and the feedback clock is above a specified value, locking and storing the frequency code once the difference between reference clock and the feedback clock is below the specified value, and de-asserting the clamp signal to switch the charge pump and the phase frequency detector in a normal working mode. - View Dependent Claims (17, 18, 19)
-
-
20. A fast locking phase-locked loop producing low jitter comprising:
-
a phase frequency detector, a charge pump, a loop filter, a first oscillator comprising odd number of inverters, configured as a low frequency open loop oscillator to generate the first current which is stable across process, voltage and temperature variation, a second oscillator comprising a scaled version of the inverters of the first oscillator, configured as a closed loop current controlled high frequency oscillator to generate the output frequency of the PLL, a frequency calibration block, configured to generate a frequency code by comparing a reference clock frequency and a feedback clock frequency, a digital to analog converter, configured to generate a second current by multiplying the first current and the frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current, wherein the frequency code is generated and stored during a training mode prior to the normal mode of the PLL, wherein the voltage output of the loop filter is clamped to a clamp voltage during the training mode.
-
Specification