Level shifter

• US 10,447,269 B1
• Filed: 05/08/2019
• Issued: 10/15/2019
• Est. Priority Date: 05/08/2019
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Zhang, Xu, Delshadpour, Siamak
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US16/406,976
• Time in Patent Office: 160 Days
• Field of Search: 326 81
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A level shifter circuit to translate a first voltage level and a second voltage level of a signal is disclosed. The level shifter circuit includes a comparator. The comparator includes an input differential transistor pair with a matched current mirror load. The level shifter also includes a parallel signal path circuit to reduce the voltage transition lag caused by the comparator, a hysteresis adjusting device and a reference voltage generator circuit to provide a reference voltage to the comparator.

Claims

1. A level shifter circuit to translate a first voltage level and a second voltage level of a signal, the level shifter circuit comprising:

a comparator including an input differential transistor pair with a matched current mirror load, wherein the input differential transistor pair includes an input side transistor;

a parallel signal path circuit to reduce a voltage transition lag caused by the comparator;

a hysteresis adjusting device; and

a reference voltage generator circuit to provide a reference voltage to a reference connected transistor that is driven by the reference voltage, wherein the hysteresis adjusting device includes a hysteresis transistor connected between a source and a drain of the reference connected transistor.

2. The level shifter circuit of claim 1, wherein the parallel signal path circuit includes an inverter.

3. The level shifter circuit of claim 1, wherein a gate of the hysteresis transistor is coupled to a drain of an input connected transistor of the comparator, wherein the input connected transistor is driven by a signal at an input port of the comparator.

4. The level shifter circuit of claim 1, wherein the comparator further includes a current limiting device coupled between a source of the input side transistor and one of a supply voltage and ground.

5. The level shifter circuit of claim 4, wherein the current limiting device is optimized to minimize a current when a level shifter circuit enable signal is off.

6. The level shifter circuit of claim 1, wherein the reference voltage generator circuit includes a first resistor and a second resister coupled in series and the first resistor coupled to a supply voltage.

7. The level shifter circuit of claim 1, further including a first switch coupled between the input differential transistor pair and one of a supply voltage and ground to disconnect power to the first switch when a level shifter enable signal is off.

8. The level shifter circuit of claim 1, further including a second switch coupled between the parallel signal path circuit and one of the supply voltage and ground to disconnect power to the parallel signal path circuit when a level shifter enable signal is off.

9. The level shifter circuit of claim 1, wherein a single supply is applied to power the level shifter.