Low power logic circuitry

• US 10,447,270 B2
• Filed: 10/01/2018
• Issued: 10/15/2019
• Est. Priority Date: 12/08/2017
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Linstadt, John Eric
• Primary Examiner(s): Kim, Seokjin
• Application Number:
  US16/148,977
• Publication Number:
  US 20190181866A1
• Time in Patent Office: 379 Days
• Field of Search: None
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

Claims

1. A combinational logic circuit within a programmable gate array, the combinational logic circuit comprising:

first input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and

first output circuitry to generate, on a first output signal line, a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal on the first node;

wherein the first input circuitry, the first node, and the first output circuitry are integrated within a first logic cell of the gate array and wherein the first node has a substantially lower capacitance than the first output signal line.

2. The combinational logic circuit of claim 1 further comprising:

second input circuitry to receive the first output signal and to generate, in response to the transitions of the first output signal, a second localized signal that transitions between the upper and lower voltages of the second voltage domain; and

second output circuitry to generate a second output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the second localized signal.

3. The combinational logic circuit of claim 2 further comprising third input circuitry to receive a second input signal and to generate, in response to the transitions of the second input signal, a third localized signal that transitions between the upper and lower voltages of the second voltage domain, and wherein the second output circuitry to generate the second output signal comprises circuitry to generate the second output signal based on the second localized signal and based on the third localized signal.

4. The combinational logic circuit of claim 2 wherein the second input circuitry and second output circuitry are integrated within a second logic cell of the programmable gate array, the second input circuitry being coupled to the first output line to receive the first output signal from the first output circuitry.

5. The combinational logic circuit of claim 2 wherein a difference between the upper and lower voltages of the second voltage domain exceeds a difference between the upper and lower voltages of the first voltage domain by the factor of six or more.

6. The combinational logic circuit of claim 1 wherein the first output circuitry comprises a first transistor having a gate terminal coupled to receive the first localized signal and coupled source-to-drain between the upper voltage of the first voltage domain and an output node on which the first output signal is generated.

7. The combinational logic circuit of claim 6 wherein the first localized signal comprises a differential signal having true and complement component signals, wherein the gate terminal of the first transistor is coupled to receive the true component signal, and wherein the first output circuitry further comprises a second transistor coupled-source-to-drain between the lower voltage of the first voltage domain and the output node and having a gate terminal coupled to receive the complement component signal.

8. The combinational logic circuit of claim 6 wherein the first transistor has a threshold voltage at intended operating temperature, and wherein the upper and lower voltages of the first voltage domain differ by at least twice the threshold voltage.

9. The combinational logic circuit of claim 8 wherein the threshold voltage at intended operating temperature is less than 25 millivolts.

10. The combinational logic circuit of claim 8 wherein the upper and lower voltages of the second voltage domain differ by more than four times the threshold voltage at intended operating temperature.

11. A method of operation in a combinational logic circuit within a programmable gate array, the method comprising:

receiving, via first input circuitry, a first input signal that transitions between upper and lower voltages of a first voltage domain

generating, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and

generating, within first output circuitry, a first output signal that transitions on a first output signal line between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal;

wherein the first input circuitry, the first node, and the first output circuitry are integrated within a first logic cell of the programmable gate array and wherein the first node has a substantially lower capacitance than the first output signal line.

12. The method of claim 11 further comprising:

receiving the first output signal via second input circuitry generating, in response to the transitions of the first output signal, a second localized signal that transitions between the upper and lower voltages of the second voltage domain; and

generating, within second output circuitry, a second output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the second localized signal.

13. The method of claim 12 further comprising receiving a second input signal via third input circuitry and generating, in response to the transitions of the second input signal, a third localized signal that transitions between the upper and lower voltages of the second voltage domain, and wherein generating the second output signal comprises generating the second output signal based on the second localized signal and based on the third localized signal.

14. The method of claim 12 wherein the second input circuitry and second output circuitry are integrated within a second logic cell of the programmable gate array, the second output circuitry being coupled to the first output line to receive the first output signal from the first output circuitry.

15. The method of claim 11 wherein generating the first output signal based at least in part on the transitions of the first localized signal comprises (i) switchably coupling the upper voltage of the first voltage domain to the first output line in response to a transition of the first localized signal to a voltage corresponding to the upper voltage of the second voltage domain, and (ii) switchably decoupling the upper voltage of the first voltage domain from the first output line in response to a transition of the first localized signal to a voltage corresponding to the lower voltage of the second voltage domain.

16. The method of claim 15 wherein generating the first output signal based at least in part on the transitions of the first localized signal further comprises (i) switchably coupling the lower voltage of the first voltage domain to the first output line when the first localized signal transitions to the voltage corresponding to the lower voltage of the second voltage domain, and (ii) switchably decoupling the lower voltage of the first voltage domain from the first output line when the first localized signal transitions to the voltage corresponding to the upper voltage of the second voltage domain.

17. The method of claim 15 wherein switchably coupling the upper voltage of the first voltage domain to the first output line comprises switching a first transistor to a conducting state, the first transistor having a threshold voltage not more than half the voltage difference between the upper and lower voltages of the first voltage domain.

18. The method of claim 17 wherein the threshold voltage is less than 25 millivolts.

19. The method of claim 17 wherein the upper and lower voltages of the second voltage domain differ by a voltage more than twice the voltage by which the upper and lower voltages of the first voltage domain differ.

20. The method of claim 11 wherein generating the first localized signal that transitions between upper and lower voltages of the second voltage domain comprises generating the first localized signal within a cryogenic environment.

21. A combinational logic circuit within a programmable gate array, the combinational logic circuit comprising:

means for receiving a first input signal that transitions between upper and lower voltages of a first voltage domain

means for generating, in response to the transitions of the first input signal, a first localized signal that transitions, on a first node, between upper and lower voltages of a second voltage domain, the upper and lower voltages of the second voltage domain differing more than the upper and lower voltages of the first voltage domain; and

means for generating, on a first output signal line, a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal;

wherein the means for receiving the first output signal, the first node, and the means for generating the first output signal are integrated within the first logic cell of the programmable gate array and wherein the first node has a substantially lower capacitance than the first output signal line.