Three dimensional integrated-circuits

• US 10,447,272 B2
• Filed: 02/09/2018
• Issued: 10/15/2019
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Campbell, Shaun M
• Application Number:
  US15/893,537
• Publication Number:
  US 20180167071A1
• Time in Patent Office: 613 Days
• Field of Search: None
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Claims

1. A device, comprising:

a programmable circuit including programmable logic and operable to receive a plurality of input programming logic values to set the programmable logic; and

a functionality determination circuit in a stack arrangement relative to the programmable circuit and operable to provide the plurality of input programming logic values;

wherein if the functionality determination circuit comprises a programmable memory coupled to the programmable circuit, the programmable memory is operable to program the programmable circuit with the plurality of input programming logic values; and

wherein if the functionality determination circuit comprises a wire pattern hard-wired to the programmable circuit, the wire pattern is operable to hard-wire the programmable circuit with the plurality of input programming logic values.

2. The device of claim 1, further comprising:

a first multi-layered module including the programmable circuit; and

a second multi-layered module including the functionality determination circuit, wherein the first and second multi-layered modules are in the stack arrangement.

3. The device of claim 2, further comprising:

a third multi-layered module including a routing circuit coupled to the programmable circuit, wherein the third multi-layered module is in the stack arrangement with the first and second multi-layered modules.

4. The device of claim 3, wherein the second multi-layered module depends on at least one of the first multi-layered module and the third multi-layered module to communicate external to the second multi-layered module.

5. The device of claim 2, further comprising:

a plurality of electrical connections located at a plurality of predetermined positions between the first multi-layered module and the second multi-layered module.

6. The device of claim 5, wherein the functionality determination circuit comprises a programmable memory and the plurality of electrical connections are operable to communicate the plurality of input programming logic values from the programmable memory to the programmable circuit.

7. The device of claim 5, wherein the functionality determination circuit comprises a wire pattern and the plurality of electrical connections are operable to hard-wire the plurality of input programming logic values from the wire pattern to the programmable circuit.

8. A method, comprising:

forming a programmable circuit including programmable logic that is set by a plurality of input programming logic values; and

forming a functionality determination circuit in a stack arrangement relative to the programmable circuit, wherein said forming the functionality determination circuit includes;

if the functionality determination circuit comprises a programmable memory, coupling the programmable memory to the programmable circuit to program the plurality of input programming logic values; and

if the functionality determination circuit comprises a wire pattern, hard-wiring the wire pattern to the programmable circuit to hard-wire the plurality of input programming logic values.

9. The method of claim 8, wherein said forming the programmable circuit comprises:

forming a first multi-layered module including the programmable circuit.

10. The method of claim 9, wherein said forming the functionality determination circuit further comprises:

forming a second multi-layered module including the functionality determination circuit, wherein the first and second multi-layered modules are in the stack arrangement.

11. The method of claim 10, further comprising:

forming a third multi-layered module including a routing circuit coupled to the programmable circuit, wherein the third multi-layered module is in the stack arrangement with the first and second multi-layered modules.

12. The method of claim 11, wherein the second multi-layered module depends on at least one of the first multi-layered module and or the third multi-layered module to communicate external to the second multi-layered module.

13. The method of claim 10, further comprising:

forming a plurality of electrical connections at a plurality of predetermined positions between the first multi-layered module and the second multi-layered module.

14. The method of claim 13, further comprising:

if the functionality determination connections comprises a programmable memory, using the plurality of electrical connections to communicate the plurality of input programming logic values from the programmable memory to the programmable circuit.

15. The method of claim 13, further comprising:

if the functionality determination circuit comprises a wire pattern, using the plurality of electrical connections to hard-wire the plurality of input programming logic values from the wire pattern to the programmable circuit.

16. A method, comprising:

forming a device including a plurality of stacked layers and programmable logic that is set by a plurality of input programming logic values; and

setting the programmable logic, wherein said setting includes;

if the plurality of stacked layers comprise a programmable memory layer and a programmable layer including the programmable logic, coupling the programmable memory layer to the programmable layer to program the plurality of input programming logic values; and

if the plurality of stacked layers comprise a hard-wire layer and the programmable layer, hard-wiring the hard-wire layer to the programmable layer to hard-wire the plurality of input programming logic values.

17. The method of claim 16, wherein the plurality of stacked layers comprise a routing layer including a routing circuit coupled to the programmable logic.

18. The method of claim 16, wherein said forming said device comprises:

using one of a first set of masks associated with the programmable memory layer and a second set of masks associated with the hard-wire layer.

19. The method of claim 16, wherein said forming said device comprises:

forming, at a plurality of predetermined positions of the device, a plurality of layer interconnects to route the plurality of input programming logic values.

20. The method of claim 16, wherein the programmable logic comprises at least one of a pass gate logic, a multiplexer logic, a truth table logic, and an AND/OR logic.