Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
First Claim
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1. A field-programmable-gate-array (FPGA) IC chip comprising:
- a programmable logic block, configured to be programed to perform a logic operation, comprising;
a plurality of input points for a first input data set for the logic operation;
a plurality of first non-volatile memory cells configured to store a plurality of resulting values of a look-up table (LUT), each of the plurality of first non-volatile memory cells comprising;
a floating-gate N-type MOS transistor having a gate terminal, comprising a first P-type fin protruding from a P-type silicon substrate of the field-programmable-gate-array (FPGA) IC chip and extending in a first direction;
a floating-gate P-type MOS transistor having a gate terminal coupling to the gate terminal of the floating-gate N-type MOS transistor, comprising an N-type well in the P-type silicon substrate and a first N-type fin protruding from the N-type well and extending in the first direction;
an interconnect extending from the first P-type fin to the first N-type fin in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first P-type fin and a top and two opposite sidewalls of the first N-type fin; and
an oxide layer over the P-type silicon substrate, between the interconnect and the first P-type fin and between the interconnect and the first N-type fin,wherein the interconnect connects the gate terminals of the floating-gate N-type MOS transistor and the floating-gate P-type MOS transistor, and wherein the interconnect is floating;
a circuit configured to select, in accordance with the first input data set, a resulting value from the plurality of resulting values of the look-up table (LUT) as an output data for the logic operation; and
an output point for the output data for the logic operation.
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Abstract
A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
82 Citations
20 Claims
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1. A field-programmable-gate-array (FPGA) IC chip comprising:
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a programmable logic block, configured to be programed to perform a logic operation, comprising; a plurality of input points for a first input data set for the logic operation; a plurality of first non-volatile memory cells configured to store a plurality of resulting values of a look-up table (LUT), each of the plurality of first non-volatile memory cells comprising; a floating-gate N-type MOS transistor having a gate terminal, comprising a first P-type fin protruding from a P-type silicon substrate of the field-programmable-gate-array (FPGA) IC chip and extending in a first direction; a floating-gate P-type MOS transistor having a gate terminal coupling to the gate terminal of the floating-gate N-type MOS transistor, comprising an N-type well in the P-type silicon substrate and a first N-type fin protruding from the N-type well and extending in the first direction; an interconnect extending from the first P-type fin to the first N-type fin in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first P-type fin and a top and two opposite sidewalls of the first N-type fin; and an oxide layer over the P-type silicon substrate, between the interconnect and the first P-type fin and between the interconnect and the first N-type fin, wherein the interconnect connects the gate terminals of the floating-gate N-type MOS transistor and the floating-gate P-type MOS transistor, and wherein the interconnect is floating; a circuit configured to select, in accordance with the first input data set, a resulting value from the plurality of resulting values of the look-up table (LUT) as an output data for the logic operation; and an output point for the output data for the logic operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A field-programmable-gate-array (FPGA) IC chip comprising:
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a switch; and a plurality of non-volatile memory cells configured to store a plurality of programming codes configured to control the switch, each of the plurality of non-volatile memory cells comprising; a floating-gate N-type MOS transistor having a gate terminal, comprising a first P-type fin protruding from a P-type silicon substrate of the field-programmable-gate-array (FPGA) IC chip and extending in a first direction; a floating-gate P-type MOS transistor having a gate terminal coupling to the gate terminal of the floating-gate N-type MOS transistor, comprising an N-type well in the P-type silicon substrate and a first N-type fin protruding from the N-type well and extending in the first direction; an interconnect extending from the first P-type fin to the first N-type fin in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first P-type fin and a top and two opposite sidewalls of the first N-type fin; and an oxide layer over the P-type silicon substrate, between the interconnect and the first P-type fin and between the interconnect and the first N-type fin, wherein the interconnect connects the gate terminals of the floating-gate N-type MOS transistor and the floating-gate P-type MOS transistor, and wherein the interconnect is floating. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification