Phase adjusting circuit, inverter circuit, and power supply system

• US 10,447,281 B2
• Filed: 02/06/2018
• Issued: 10/15/2019
• Est. Priority Date: 03/31/2017
• Status: Active Grant

• Current Assignee: Sumida Corporation
• Original Assignee: Sumida Corporation
• Inventors: Miyazaki, Hiroyuki
• Primary Examiner(s): Laxton, Gary L
• Assistant Examiner(s): Rivera-Perez, Carlos O
• Application Number:
  US15/889,683
• Publication Number:
  US 20180287619A1
• Time in Patent Office: 616 Days
• Field of Search: 363 15- 2103, 363 39- 43, 363 47, 363 74, 363 79, 363 95- 98, 363123, 363131-134, 323205-214, 323217-219, 323235, 323236, 323266, 323271-275, 323280-286, 323298, 323304, 323311-313, 323351, 331 12, 331 16, 331 18, 331 23, 331 25, 331 36 R, 327147-163
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 7/4815 Resonant converters H02M7/4811 and H02M7/4826 take precedence
• CPC Class Codes: H02M 7/4818 with means for adaptation of resonance frequency, e.g. by modification of capacitance or inductance of resonance circuits
• CPC Class Codes: H02M 7/5387 in a bridge configuration
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current
• CPC Class Codes: H02M 7/5395 by pulse-width modulation
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A phase adjusting circuit is provided that can highly precisely adjust frequencies throughout the entire frequency range to be dealt with. A PLL circuit includes: a reference-signal input terminal from which a reference signal is input; a feedback-signal input terminal from which a feedback signal is input; and an output terminal from which an output signal based on a phase difference between the reference signal and the feedback signal is output. A filter circuit is connected to the reference-signal input terminal and the output terminal, and causes a phase of the reference signal to be delayed when the oscillation frequency of an inverter circuit including the PLL circuit falls in a high range. A delay circuit is connected to the output terminal, and causes the output signal to be delayed when the oscillation frequency of the inverter circuit falls in a low range lower than the high range.

Claims

1. An inverter circuit comprising:

a phase adjusting circuit configured to adjust a phase of a current, the phase adjusting circuit including;

a phase synchronizing circuit, the phase synchronizing circuit including;

a reference-signal input terminal from which a reference signal is input;

a feedback-signal input terminal from which a feedback signal is input; and

an output terminal from which an output signal based on a phase difference between the reference signal and the feedback signal is output;

a filter circuit that is connected to the reference-signal input terminal and the output terminal, the filter circuit being configured to receive the output signal and output the reference signal, and the filter circuit being configured to cause a phase of the reference signal to be delayed when an oscillation frequency of the inverter circuit falls to a first level; and

a delay circuit that is connected to the output terminal, the delay circuit being configured to receive the output signal, and the delay circuit being configured to change a time constant so as to delay the output signal when the oscillation frequency of the inverter circuit falls to a second level that is lower than the first level,

wherein the filter circuit includes;

a first capacitive element configured to advance the phase of the current with respect to the output signal;

a coil element configured to delay the phase of the current with respect to the output signal; and

a first variable resistance element having a variable resistance value, the first variable resistance element being configured to vary a gain of the filter circuit, and

the phase of the reference signal is determine by a capacitance value of the first capacitive element, an inductance value of the coil element, a resistance value of the first variable resistance element, and an angular velocity of the current.

2. The inverter circuit according to claim 1, wherein

the delay circuit includes a second capacitive element and a second variable resistance element having a variable resistance value.

3. The inverter circuit according to claim 1, further comprising:

a drive circuit configured to convert a DC power into an alternating current; and

a control circuit configured to receive the output signal via the delay circuit, the control circuit being configured to control the drive circuit.

4. A power supply system comprising:

the inverter circuit according to claim 3; and

a load that is connected to the drive circuit, the load being configured to output electric power.

5. The power supply system according to claim 4,

wherein the control circuit is a pulse width modulation control circuit.

6. The power supply system according to claim 4,

wherein the first level is 2.0 MHz, and the second level is 1.5 MHz.

7. The power supply system according to claim 4,

wherein a difference between the first level and the second level is ⅓

of the second level.

8. The inverter circuit according to claim 3,

wherein the control circuit is a pulse width modulation control circuit.

9. The inverter circuit according to claim 3,

wherein the first level is 2.0 MHz, and the second level is 1.5 MHz.

10. The inverter circuit according to claim 3,

wherein a difference between the first level and the second level is ⅓

of the second level.

11. The inverter circuit according to claim 1,

wherein the first level is 2.0 MHz, and the second level is 1.5 MHz.

12. The inverter circuit according to claim 1,

wherein a difference between the first level and the second level is ⅓

of the second level.