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Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter

  • US 10,447,290 B2
  • Filed: 12/11/2017
  • Issued: 10/15/2019
  • Est. Priority Date: 12/11/2017
  • Status: Active Grant
First Claim
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1. A comparator circuit, comprising:

  • a first transistor configured to receive a first input;

    a second transistor configured to receive a second input;

    a third transistor coupled to a terminal of each of the first and second transistors, wherein the third transistor is configured to be controlled by a first control signal;

    a fourth transistor;

    a fifth transistor, wherein a gate of the fifth transistor is coupled to a terminal of the fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node; and

    a sixth transistor coupled between the first and fourth transistors;

    a seventh transistor coupled between the second and fifth transistors; and

    a transistor switch coupled between a node intercoupling the first and sixth transistors and a node intercoupling the second and seventh transistors;

    wherein a gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level;

    wherein the transistor switch is controlled by a second control signal having an edge that is delayed from the edge of the first control signal.

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