Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter

• US 10,447,290 B2
• Filed: 12/11/2017
• Issued: 10/15/2019
• Est. Priority Date: 12/11/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ghosh, Sovan, Kundu, Amal Kumar, Seetharaman, Janakiraman
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/837,040
• Publication Number:
  US 20190181873A1
• Time in Patent Office: 673 Days
• Field of Search: 327 50
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03M 1/089 of temperature variations
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14

Abstract

A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

Claims

1. A comparator circuit, comprising:

a first transistor configured to receive a first input;

a second transistor configured to receive a second input;

a third transistor coupled to a terminal of each of the first and second transistors, wherein the third transistor is configured to be controlled by a first control signal;

a fourth transistor;

a fifth transistor, wherein a gate of the fifth transistor is coupled to a terminal of the fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node; and

a sixth transistor coupled between the first and fourth transistors;

a seventh transistor coupled between the second and fifth transistors; and

a transistor switch coupled between a node intercoupling the first and sixth transistors and a node intercoupling the second and seventh transistors;

wherein a gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level;

wherein the transistor switch is controlled by a second control signal having an edge that is delayed from the edge of the first control signal.

2. The comparator circuit of claim 1, wherein the first, second, sixth and seventh transistors comprise p-type metal oxide semiconductor field effect transistors.

3. The comparator circuit of claim 1, further comprising:

an eighth transistor coupled to the first node, wherein a gate of the eighth transistor is coupled to the second node; and

a ninth transistor coupled to the second node, wherein a gate of the ninth transistor is coupled to the first node.

4. The comparator circuit of claim 3, further comprising a tenth transistor coupled to a terminal of each of the eighth and ninth transistors, wherein the tenth transistor is configured to be controlled by a third control signal having an edge that is delayed from a corresponding edge of the first control signal.

5. The comparator circuit of claim 1, wherein the fourth and fifth transistors comprise n-type metal oxide semiconductor field effect transistors and the eighth and ninth transistors comprise p-type metal oxide semiconductor field effect transistors.

6. A comparator circuit, comprising:

a first transistor configured to receive a first input;

a second transistor configured to receive a second input;

a third transistor coupled to a terminal of each of the first and second transistors, wherein the third transistor is configured to be controlled by a first control signal;

a fourth transistor;

a fifth transistor, wherein a gate of the fifth transistor is coupled to a terminal of the fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node; and

a sixth transistor coupled between the first and fourth transistors;

a seventh transistor coupled between the second and fifth transistors;

a first capacitor coupled in parallel with the fourth transistor;

a second capacitor coupled in parallel with the fifth transistor;

a first transistor switch coupled in parallel with the first capacitor; and

a second transistor switch coupled in parallel with the second capacitor;

wherein a gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

7. The comparator circuit of claim 6, wherein the first transistor switch is controlled by a second control signal having an edge that is delayed from the edge of the first control signal.

8. A comparator circuit, comprising:

a first transistor configured to receive a first input;

a second transistor configured to receive a second input;

a third transistor coupled to a terminal of each of the first and second transistors, wherein the third transistor is configured to be controlled by a first control signal;

a transistor switch coupled between drains of the first and second transistors;

a fourth transistor including a gate and a drain;

a fifth transistor including a gate and a drain, wherein the gate of the fifth transistor is coupled to the drain of the fourth transistor and the gate of the fourth transistor is coupled to the drain of the fifth transistor;

a sixth transistor including a drain and a gate, wherein the drains of the fourth and sixth transistors are coupled together, wherein a gate of the sixth transistor is coupled to the drain of the fifth transistor;

a seventh transistor including a drain and a gate, wherein the drains of the fifth and seventh transistors are coupled together, and wherein a gate of the seventh transistor is coupled to the drain of the fourth transistor; and

an eighth transistor coupled to a terminal of each of the sixth and seventh transistors, wherein the eighth transistor is configured to be controlled by a second control signal having an edge that is delayed from a corresponding edge of the first control signal;

wherein the transistor switch is controlled by a third control signal having an edge that is delayed from the corresponding edge of the first control signal by less of a delay that for the second control signal.

9. The comparator circuit of claim 8, further comprising a ninth transistor coupled between the first and fourth transistors and a tenth transistor coupled between the second and fifth transistors.

10. The comparator circuit of claim 9, wherein a gate of the ninth transistor and a gate of the tenth transistor are coupled together at a fixed voltage level.