Low density parity check encoder having length of 16200 code rate of 3/15, and low density parity check encoding method using the same

• US 10,447,304 B2
• Filed: 09/21/2016
• Issued: 10/15/2019
• Est. Priority Date: 08/14/2014
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Park, Sung-Ik, Kim, Heung-Mook, Kwon, Sun-Hyoung, Hur, Nam-Ho
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/272,142
• Publication Number:
  US 20170012647A1
• Time in Patent Office: 1,119 Days
• CPC Class Codes: H03M 13/036 Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
• CPC Class Codes: H03M 13/1157 Low-density generator matrices [LDGM]
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/1185 wherein the parity-check matrix comprises a part with a double-diagonal
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6552 DVB-T2
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Claims

1. A method of transmitting a broadcast signal, the method comprising:

initializing first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 3/15, and second memory;

generating the LDPC codeword corresponding to information bits by performing accumulation of at least one of bits from the first memory at parity bit addresses of the second memory, the parity bit addresses being updated using numbers of a sequence, the sequence being equivalent to a parity check matrix (PCM);

generating a transmission signal based on the LDPC codeword, the LDPC codeword including parity bits for correcting errors occurring over a physical channel; and

transmitting, using an antenna, the transmission signal over the physical channel,

wherein the sequence is expressed as follows;

2. The method of claim 1, wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.

3. The method of claim 2, wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part, that is, 3240, by a circulant permutation matrix (CPM) size corresponding to the PCM, that is, 360, and a value obtained by dividing a length of the first parity part, that is, 1080, by the CPM size.

4. The method of claim 3, wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM.