Apparatuses and methods for pipelining memory operations with error correction coding
First Claim
1. A method, comprising:
- executing a first read operation in a memory to read first read data;
determining errors in the first read data;
correcting the errors in the first read data;
pre-charging a local input-output line after the first read operation has executed;
executing a second read operation in the memory to read second read data during the determining of the errors in the first read data;
merging the corrected first read data with first write data to provide first merged data;
calculating a first new error correction code for the first merged data;
executing a first write operation to write the first merged data in the memory;
determining errors in the second read data during the merging of the corrected first read data with the first write data;
correcting the errors in the second read data;
merging the corrected second read data with second write data to provide second merged data;
calculating a second new error correction code for the second merged data; and
executing a second write operation to write the second merged data in the memory.
8 Assignments
0 Petitions
Accused Products
Abstract
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
-
Citations
19 Claims
-
1. A method, comprising:
-
executing a first read operation in a memory to read first read data; determining errors in the first read data; correcting the errors in the first read data; pre-charging a local input-output line after the first read operation has executed; executing a second read operation in the memory to read second read data during the determining of the errors in the first read data; merging the corrected first read data with first write data to provide first merged data; calculating a first new error correction code for the first merged data; executing a first write operation to write the first merged data in the memory; determining errors in the second read data during the merging of the corrected first read data with the first write data; correcting the errors in the second read data; merging the corrected second read data with second write data to provide second merged data; calculating a second new error correction code for the second merged data; and executing a second write operation to write the second merged data in the memory. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A method, comprising:
-
receiving a first data signal at a memory; reading first read data from a first address in the memory; calculating a first error correction code for the first read data; merging data from the first data signal with the first read data to generate first new data; calculating a first new error correction code for the first new data; receiving a second data signal at the memory; reading second read data from a second address in the memory during the calculating of the first new error correction code for the first new data; calculating a second error correction code for the second read data; merging data from the second data signal with the second read data to generate second new data; calculating a second new error correction code for the second new data; writing the first new data to the first address in the memory; and writing the second new data to the second address in the memory. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A method, comprising:
-
receiving a first write command at a memory; receiving a second write command at the memory; receiving a first data signal at the memory; receiving a first mask data signal at the memory; executing a first read operation at a first address in the memory after the first data signal and the first mask data signal have been received; calculating a first error correction code for data read from the first address; merging data from the first data signal with the data read from the first address to generate first new data; calculating a first new error correction code for the first new data; receiving a second data signal at the memory; receiving a second mask data signal at the memory; executing a second read operation at a second address in the memory; calculating a second error correction code for data read from the second address; merging data from the second data signal with the data read from the second address to generate second new data; calculating a second new error correction code for the second new data; executing a first write operation at the first address to store the first new data; and executing a second write operation at the second address to store the second new data. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
Specification