Robust line coding scheme for communication under severe external noises
1. A system comprising:
- a media independent interface circuitry configured to receive, from an automobile component, binary data and corresponding management information to be transmitted via a communication link;
an encoder circuitry configured to generate forward error correction (FEC) frames that contain the binary data and the management information; and
a communication interface circuitry configured to transmit the FEC frames that contain the binary data and the management information via the communication link.
A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.
View as Search Results
|Efficient ethernet multi-mode coding and modulation for twisted-pair|
Patent #US 10,644,834 B1
Current AssigneeCavium International
Sponsoring EntityMarvell International Limited
|HIGH BANDWIDTH DATA TRANSPORT SYSTEM|
Patent #US 20100329247A1
Current AssigneeLightwaves Systems Inc.
Sponsoring EntityLightwaves Systems Inc.
|Modulation Scheme for Communication Environments|
Patent #US 20090010318A1
Current AssigneeIntel Corporation
Sponsoring EntityIntel Corporation
|ALL-DIGITAL TIMING CONTROL FOR MULTI-CHANNEL FULL-DUPLEX TRANSCEIVER|
Patent #US 20090323566A1
Current AssigneeRealtek Semiconductor Corp.
Sponsoring EntityRealtek Semiconductor Corp.
|Transmitter for transmitting information data and receiver for receiving information data|
Patent #US 20070250752A1
Current AssigneeFraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
Sponsoring EntityFraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
|ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS|
Patent #US 20050099966A1
Current AssigneeRealtek Semiconductor Corp.
Sponsoring EntityRealtek Semiconductor Corp.
|Data Sending/Receiving Method with Forward Error Correction and Related Component and System for Gigabit Ethernet|
Patent #US 20110320905A1
Current AssigneeFuturewei Technologies Incorporated
Sponsoring EntityFuturewei Technologies Incorporated
- 1. A system comprising:
a media independent interface circuitry configured to receive, from an automobile component, binary data and corresponding management information to be transmitted via a communication link; an encoder circuitry configured to generate forward error correction (FEC) frames that contain the binary data and the management information; and a communication interface circuitry configured to transmit the FEC frames that contain the binary data and the management information via the communication link.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- 11. A system comprising:
a physical media communication interface configured to receive data from an automobile component over a physical media; converter circuitry configured to convert the data into a forward error correction (FEC) frame that comprises a plurality of symbols; decoder circuitry configured to decode, from the plurality of symbols, a plurality of data symbols and a management symbol; and a media independent interface configured to transmit the plurality of data symbols and the management symbol to another automobile component for further processing.
- View Dependent Claims (12, 13, 14, 15, 16, 17)
- 18. A method comprising:
generating, by a physical coding sublayer (PCS) framer circuitry, PCS blocks based at least in part on received MAC layer data; aggregating, by an encoder circuitry, a predetermined number of PCS blocks and operations, administration, and maintenance (OAM) bits to generate aggregated PCS blocks; scrambling, by a data scrambler circuitry, the aggregated PCS blocks to generate scrambled aggregated PCS blocks, wherein the data scrambler circuitry does not scramble the OAM bits of the aggregated PCS blocks; and transmitting the aggregated scrambled PCS blocks via a communication link.
- View Dependent Claims (19, 20)
This application is a continuation application of U.S. application Ser. No. 14/705,608, filed May 6, 2015, now issued as U.S. Pat. No. 9,819,444, which claims priority to Provisional Application No. 61/991,331, filed May 9, 2014, which are incorporated by reference in their entirety.
This disclosure relates to, networking hardware used for communication.
High speed data networks form part of the backbone of what has become indispensable worldwide data connectivity. Within the data networks, network devices such as switching devices direct data packets from source ports to destination ports, helping to eventually guide the data packets from a source to a destination. Improvements in packet handling, including improvements in path resolution, will further enhance performance of data networks.
The embodiments may be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale. Moreover, in the figures, like-referenced numerals designate corresponding parts throughout the different views.
In certain communication applications under severe noises, such as the IEEE 802.3bp 1000BASE-T1 automotive Ethernet PHY, it may be desirable to have a robust system while at the same time achieve target high speed data rates, even under severe external noises. The external noises may be due to narrow band interferences, mechanical vibrations, electrostatic discharges, or other sources. Furthermore the characteristics of these noises may rapidly change in time. It may be further desirable to maintain a robust system and minimize interruptions to the communication link.
The disclosure described below provides networking hardware comprising circuitry using a robust line coding scheme for communication under severe external noises. The scheme uses a non-complex bit-to-symbol mapping, the forward error correction (FEC) coding, and an additive bit scrambler after the FEC. The line coding scheme may be utilized in various communication environments, such as in the automobile 1000 Mbits per second Ethernet PHY over single unshielded twisted pair (UTP) IEEE 802.3bp application. The scheme may be extended to applications other than 802.3bp, for example to 100 m industrial Ethernet PHY applications. Further, instead of a single UTP cable, the scheme may be extended to 2 or more pairs of UTP cables, or to coaxial or shielded twisted pair (STP) cable types and/or other communication links.
The line coding scheme may use a signal constellation for coded data being communicated using the UTP. Further, the same signal constellation, or another signal constellation may be used for training during a link-up process. Separate signal constellations may be used during a low power idle (LPI) mode. Example LPI and stream markers used during the communication using the line coding scheme are also described. Further, example clock structure(s) that may be used for interfacing a Gigabit Media Independent Interface (GMII) and a Medium Dependent Interface (MDI) or a Medium Dependent Interface Crossover (MDI-X) is also described.
For example, the device 110 and device 120 may be devices that are part of a driver assistance system, and/or a vehicle infotainment system. For example, the device 110 may be automobile component. The automobile component may be, for example, a sensor system such as a video camera, a sound navigation and ranging (SONAR) system, a tire pressure monitoring system, a brake sensor, or any other sensor of an automobile. In another example, the device 110 may be a media player such as a radio, a satellite radio, a video player and/or an audio player. In another example, the device 110 may be an automobile component such as a navigation system. The device 110 may be other sources of data in an automobile environment in other examples. The device 120 may be a device that receives data from the device 110. For example, the device 120 may be another automobile component such as a display device. In other examples, the device 120 may be any of the devices listed above receiving data from another data source. For example, the navigation system may be a data receiver when receiving instructions from controls in the automobile, the controls acting as a data source in this case.
The MAC-A 112 and MAC-B 122 may include circuitry that implements link layer functions of the network communication protocols used by the communication setup 100. For example, operations in the link layer, or sometimes referred to as data link layer, may include establishment and control of logical links between devices on a network. The MAC-A 112 and MAC-B may facilitate encapsulation and/or deciphering data into frames that are sent and/or received over the communication link 150. The MAC-A 112 and MAC-B 122 may further identify the frames with particular destination address, such as the MAC address of the destination. They may further detect and correct errors in data received, for example by performing cyclic redundancy check (CRC). The MAC-A 112 is an interface between the device 110 and the PHY-A 118. The MAC-B 122 is an interface between the device 120 and the PHY-B 128.
The communication link 150 may be a UTP cable or of other cable types. In an example, the communication link 150 may be up to 15 meters long. The data from the device 110 and device 120 may be communicated across the communication link 150. The communication link 150 may be exposed to several external sources of noise that may corrupt the data being transmitted. For example, the communication link 150 may experience burst noises that are typically concentrated in time. Alternatively or in addition, the communication link 150 may experience Narrow Band interferences (NBI) that are noises concentrated in a particular frequency range, and may visually be similar to a sinusoidal wave. In another example, the communication link 150 may experience other noises such as Additive White Gaussian Noise (AWGN). It may be desirable to mitigate the effects of external noises using the PHY circuitry.
The PHY circuitry 200 provides technical solutions to achieve desired robust transmission of data, such as IEEE 802.3 or Ethernet data, at a predetermined target rate, such as 1000 Mbits per second in an automobile environment. The PHY circuitry 200 may implement a line coding scheme. The line coding scheme may be configured to convert data from the MAC circuitry in a predetermined format, for example symbols of a predetermined length. Based on the line coding scheme, the PHY circuitry 200 may be configured, or adjusted to transmit the generated symbols at a predetermined baud rate to achieve a predetermined target data transmission rate. For example, to achieve data transfer rate of 1000 Mbits per second, the PHY circuitry 200 may generate symbols that are 9 bits long, apply Reed-Solomon FEC encoding, apply 3 bits to 2 PAM3 symbols mapping, and operate at a 750 MHz baud rate. The PHY circuitry may perform forward error correction when receiving the symbols so that the communication is robust and meets a specified error threshold.
The PHY circuitry 200 may include circuitry such as a transmitter 201, a receiver 203, a media independent interface (MII) 205, an echo canceller 207, a hybrid 210, and a link interface 209.
The media independent interface 205 may be a communication interface that connects the PHY circuitry 200 with the MAC circuitry. The media independent interface may be a reduced media-independent interface, a gigabit media-independent interface (GMII), a reduced gigabit media-independent interface, a serial gigabit media-independent interface (SGMII), or any other type of media independent interface.
The hybrid 210 may be analog circuitry that cancels the transmitted signals that are coupled into the received signals. For example, the hybrid 210 may reduce electric signal reflections due to transmission and reception of signals over the same communication link 150.
The echo canceller 207 may be circuitry that facilitates mitigation of residual reflected signals from the transmitter 201. For example, the echo canceller 207 may further reduce remnant transmit signal reflections after cancellation by the hybrid 210.
The link interface 209 may be a communication interface that connects the PHY circuitry 200 with the communication link 150. For example, the link interface 209 may be a two-pin connector for single pair automotive Ethernet, a registered jack (RJ) type connecter such as a RJ45 connector, a RJ48 connecter, a RJ61 connecter, or any other type of communication link interface. The link interface 209 may facilitate transmission and reception of data via the communication link 150 using a variable input/output voltage range.
The transmitter 201 may be circuitry that facilitates transmission of data via the communication link 150. The transmitter 201 may facilitate conversion of digital input data received from the media independent interface 205 to analog output voltage levels transmitted via the hybrid 210 and the link interface 209. The transmitter 201 may convert the input data at a predetermined rate to meet the predetermined data transmission rate. In an example, the transmitter 201 may include a physical coding sublayer (PCS) framer 212, a data encoder 215, a transmission data scrambler 218, a data mapper 221, and an analog front end transmitter (AFE TX) 230.
The receiver 203 may be circuitry that facilitates reception of data via the communication link 150. The receiver 203 may facilitate conversion of analog input voltage levels received via the link interface 209 and hybrid 210 to digital data provided to the MAC circuitry via the media independent interface 205. The receiver 203 may convert the analog voltage levels at a predetermined rate to meet the predetermined data transmission rate at which the analog signals may be received. In an example, the receiver 203 may include an analog front end receiver (AFE RX) 250, a feed forward equalizer (FFE) 262, a decision feedback equalizer (DFE) 265, a slicer 268, a data de-mapper 271, a data de-scrambler 274, a data decoder 277, and a PCS de-framer 280.
The PCS framer 212 may receive the input data from the MAC circuitry via the media independent interface 205. (304) The PCS framer 212 may be circuitry that converts the input data into PCS frames. The input data may be binary data that is in the form of bits (for example 0, 1). The bits may be received in collections. For example,
The PCS framer 212 may convert the input data and the header bits into blocks of a predetermined size. (306) For example, the PCS framer 212 may be an 80/81 converter that receives 80 bits as input data and outputs a corresponding 81 bits. For example, the 80/81 converter may aggregate ten 8-bit blocks to output corresponding 81 bits that may include one bit representative of header information for the aggregated bits. In an example, the PCS framer 212 may output an 81-bit block that contains the aggregated input data and the header information. The PCS framer 212 may send the output block to the data encoder 215.
The data encoder 215 may aggregate blocks from the PCS framer 212 along with management bits, such as operation, administration, and maintenance (OAM) bits. (308) The OAM bits may be used by a communication standard or protocol to identify information such as related to monitoring and troubleshooting the communication setup 100. For example, the OAM bits may be Ethernet OAM (EOAM) bits. The OAM bits may be part of a protocol for installing, monitoring, and troubleshooting the network. In an example, the OAM bits may be received from an optional sublayer device in the data link layer of the OSI model, such as specified in the IEEE 802.1ag, or the ITU-T Y.1731, or other similar standards or specifications.
The data encoder 215 may aggregate a predetermined number of blocks from the PCS framer 212 and a predetermined number of OAM bits. In an example, the data encoder 215 may aggregate 45 81-bit blocks from the PCS framer 212. In addition, the data encoder 215 may receive and aggregate nine (9) OAM bits. Thus, the example data encoder may aggregate 45×81+9=3,654 bits.
The data encoder 215 may process the bits from the aggregated blocks and the OAM bits to output one or more FEC frames. (310) The data encoder may be, for example, a Reed-Solomon (RS) encoder. Accordingly, in this example, a FEC frame may be referred to as an RS frame, or an RS-FEC frame. A group of binary bits in the FEC frame may be defined as a symbol, such as an RS symbol. For example, the RS symbol may be nine (9) bits long and the RS-FEC frame may include multiple RS symbols. The data encoder 215 may select the size of the FEC frame. For example, the size of the FEC frame may be based on a target transmission rate across the communication link 150. Alternatively or in addition, the size of the FEC frame may be based on the number of OAM bits. In another example, the OAM bits aggregated by the data encoder 215 may be based on the predetermined size of the FEC frame. The generated FEC frames may contain some data symbols, which are referred to as RSD symbols. In addition, the data encoder 215 may generate parity check symbols, which are referred to as RSC symbols. Data bits received from the aggregated PCS framer outputs and the OAM bits may be considered as the RSD symbols.
For example, in the above case the data encoder 215 may generate an RS-FEC frame containing 450 total RS symbols, with 406 RSD symbols and 44 RSC symbols, and each symbol being 9 bits long. The RS encoder may forward the FEC frames to the data scrambler 218.
The data scrambler 218 may scramble the RS-FEC output frames. (312) The scrambling may facilitate avoiding long sequences of bits of the same value or of repeating bit patterns. Consequently, the scrambling may also facilitate timing the data accurately at the PHY circuitry 200 that receives the data without using redundant line coding. Additionally, the scrambling may reduce unwanted spurs in the transmit power spectral density measured in the frequency domain.
The data scrambler 218B may exchange an initial state with a corresponding de-scrambler at the receiver. The data scrambler 218B may continuously run once started. Thus, no synchronizing bit patterns are transmitted (or received) in case of the data scrambler 218B. Accordingly, the de-scrambler at the receiver'"'"'s PHY circuitry may not be affected by bit errors, as long as clock timing remains locked. The scrambled FEC frames from the data scrambler 218B may be forwarded to the data mapper 221.
The data mapper 221 may convert the scrambled FEC frames to pulse amplitude modulation (PAM) symbols. (314) For example, the data mapper may be a three-binary-to-two-ternary (3B2T) mapper that maps 3 binary bits into 2 PAM symbols. The PAM symbols may be based on a scheme such as a PAM3 constellation.
The AFE TX 230 may facilitate conversion of digital data to analog signals. The AFE TX may output the analog signals to the hybrid 210 and link interface 209, which may further transmit the signal over the communication link 150. In an example, the AFE TX 230 may include a digital-to-analog converter (DAC) 224, and a transmission analog filter 227. The DAC 224 may convert data from digital to analog form. The transmission analog filter 227 may filter the electronic signals prior to transmission via the communication link 150. The DAC 224 may map a digital signal output by the data mapper 221 to a predetermined voltage level. For example, the data mapper 221 may convert the binary data to ternary data. Ternary data may be a base 3 system. In an example, the binary data with values 0 and 1 may be converted to balanced ternary data with values −1, 0, and 1. Subsequently, the PMA interface 230 may map ternary data (1, 0, and −1) to three distinct voltage levels such as −0.5V, 0V, and +0.5V.
The PHY circuitry 200, thus, may implement a line coding scheme to generate symbols using the data encoder 215, the data scrambler 218, and the data mapper 221. The PHY circuitry 200 may be configured to implement the line coding scheme according to a target data transmission rate.
The line coding scheme described may be used by a system such as IEEE 802.3bp 1000BASE-T1 PHY or any other signaling protocol. The PCS may generate continuous code-group sequences that a Physical Medium Attachment Sublayer (PMA) transmits over the communication link 150, such as a twisted wire pair, a coaxial cable, or other types of cables.
The PHY circuitry 200 may be configured to implement the line coding scheme according to several other factors. For example, the line coding scheme may provide a mapping between the FEC frame and data that is transmitted as PAM symbols across the communication link 150. Alternatively or in addition, the scheme may provide an algorithmic mapping and inverse mapping from data to PAM symbols. The scheme may facilitate detection and/or communication of uncorrelated symbols in the transmitted symbol stream. There may be no correlation between symbol streams traveling in both directions using the coding scheme.
Alternatively or in addition, the line coding scheme may provide an ability to signal the status of a local receiver to the PHY circuitry 200 to indicate that the local receiver is not operating reliably and should be retrained. Further yet, the line coding scheme may facilitate signaling a request to the PHY circuitry 200 to enter the LPI mode. The line coding scheme may also facilitate signaling the PHY circuitry 200 to exit the LPI mode and return to normal operation. The PHY circuitry 200 may also be signaled that an update of the local receiver state (such as, timing recovery, adaptive filter coefficients) has completed. The line coding scheme may facilitate the system to automatically detect and correct for incorrect polarity in the connections.
The mapper may be implemented by the transmitter 201 of the PHY, such as a 1000BASE-T1 compliant PHY for automobile application. The data mapper may assign 3 bits to 2 ternary symbols from a 2D PAM3 constellation. The (0, 0) point in the center may be either unused, or used for Start-of-Stream Delimiter (SSD) and/or End-of-Stream Delimiter (ESD) and/or Low-Power-IDLE (LPI) or any other special control signal. When the (0, 0) point is used for such purposes the line coding scheme may provide a short mapping sequence for data encoding and decoding and may balance the bit assignment with no DC component. The line coding scheme may have a low Peak Average Rate (PAR) such as 1.25 DB before Power Spectral Density (PSD) shaping. The Euclidean distance between some of the constellation points may improve immunity for noise vectors. The line coding scheme may use additional power to mitigate error propagation. Alternatively, the line coding scheme may use additional Euclidean distance to mitigate error propagation.
The constellation 700 may involve idle symbols transmitted over 4 transmit symbols using 4 scrambler bits. The constellation may provide a short mapping sequence and a balance assignment with no DC component. Further, the constellation 720 may provide increased Euclidean distance compared to data constellation. The 00 point may be left for SSD/ESD, LPI, or any other special control symbol. Further line coding scheme using 2D PAM3 symbols may facilitate the PHY circuitry 200 to use the same average and same peak power as data to maintain PSD limit and emission desired levels. The 720 constellation may be used for signaling a start of stream or an end of stream signal (SSD/ESD). The 00 point may be used as marker indication. In order to reduce false detection, 00 may be repeated (two or three times). Subsequent PAM2 symbols carry the corresponding SSD/ESD message. Redundant PAM2 symbols may be added to improve detection in noise. The SSD/ESD markers may allow going in and out of Idle mode without additional latency. The 740 constellation may be used for low power and low emission idle modes. Constellation 740 may enable fast recognition of LPI mode without requiring additional handshaking between two sides (such as network communication devices) of the communication link. This may further facilitate fast refresh periods for improved tracking as well as low emission idle (for example refresh periods faster than 10 uS). The emission may be measured on 100 KHz BW. Thus, using constellations such as 740 constellation, the line coding scheme using 2D PAM3 symbols may provide options to go in and out of LPI mode with little or no latency. The constellation 760 may be a training constellation. The constellation may involve the largest minimum distance to provide a robust link up on strong noise presence. Further the line coding scheme using 2D PAM3 symbols may provide a single dimensional mapping, so that no symbol synchronization may be performed with blind equalization. Further, line coding scheme using 2D PAM3 symbols may facilitate balancing assignment with no DC component. Further yet, using the 2D PAM3 constellations of the line coding scheme may facilitate the system that includes the PHY circuitry 200 to use the same DAC levels and PSD shaping as in data mode.
For example, the PCS framer 212 may be setup to convert ten 8-bit words (80 bits) from the MAC layer data into 81-bit PCS blocks 810. An 81-bit PCS block may include the 80 bits of the MAC layer data and a corresponding header bit. The data encoder 215 may aggregate 45 81-bit PCS blocks 810 and convert them into 9-bit RS symbols 820. In this case input to the data encoder 215 may be the 405 RS data symbols 820 corresponding to the 45 blocks of 81-bit PCS block 810. In addition, the data encoder 215 may encode an OAM RS symbol 830 corresponding to OAM bits. In addition, the data encoder 215 may generate 44 RSC symbols 840 for parity check. Thus, the RS encoder may output 4050 bits corresponding to the 450 9-bit RS symbols generated.
The data scrambler 218 may scramble the 4050 bits output by the data encoder 215. The scrambled data 850 output by the data scrambler 218, thus, includes 4050 bits based on the 4050 bits output by the data encoder 215. The data mapper 221 may be a 3B2T data mapper that converts 3-bits of the scrambled data 850 into ternary data 860 that includes 2-ternary symbols based on a predetermined mapping scheme, such as the table 620. The data mapper 221, in this case, may generate 2700 2D-PAM3 symbols corresponding to the scrambled data 850. The AFE TX 230 may convert the 2D-PAM3 symbols to corresponding voltage levels and transmitted across the communication link 150. Thus, the MAC layer data is transformed into the transmitted voltage levels.
The combination of 9 bits out of the PCS blocks 810 into RS symbols may be expressed as a Galois Field (GF) polynomial of a primitive element in the field. For example, a GF polynomial for the converting between 9 bits and a RS symbol is illustrated in the conversion 800.
The AFE RX 250 may comprise a programmable gain amplifier (PGA) and an analog to digital converter (ADC) that converts the analog signals received from the hybrid 210 and link interface 209 into digital data, such as in the form of binary words. The converted digital data may be further processed by the echo canceller 207 to remove the residual reflections of the transmit signals. The digital data may be further equalized by the FFE 262, DFE 265, and slicer 268. The FFE 262 may be a finite impulse response (FIR) filter and that uses voltage levels of the received data associated with previous and future symbols to correct the voltage level of the current symbol. The DFE 265 may further equalize residual linear distortions contributed by the previous symbols. Finally the slicer 268 may make decisions on the received data based upon the equalized signal. In an example, the outputs from the DFE 265 and the FFE 262 may be added together at an adder and the result provided to the slicer 268. The slicer 268 may be responsive to the received signals at its input, and outputs the nearest symbol value from the constellation of allowed discrete levels, for example as shown in constellation 610. The slicer 268, thus, provides the PAM symbols in digital format.
The input to the data de-mapper 271 thus comprises received PAM symbols, such as the 2D-PAM3 symbols from the transmitter 201, of link partner PHY circuitry 200. The received PAM3 symbols may be arranged in predetermined groups that match to the RS-FEC frame boundaries at the transmitter. For example, the data may be received in groups of 2700 2D-PAM3 symbols.
The data de-mapper 271 may receive the PAM symbols output by the slicer 268. The data de-mapper 271 may be circuitry that reverses the mapping scheme used by the data mapper 221. For example, the data de-mapper 271 may use the mapping table 620 to map the 2D-PAM3 symbols back to 3 bits of data. In an example, the data de-mapper 271 may be a 3B2T de-mapper, which converts 2 ternary data into 3 bits of binary data. In the above example, the data de-mapper may map 2700 PAM3 symbols and output 4050 bits.
The output of the data de-mapper 271 may be processed by the data de-scrambler 274. The data de-scrambler 274 may be an additive de-scrambler with identical implementation as the data scrambler 218. During the initial link up process the two PHYs may exchange settings and preferences by utilizing an information exchange protocol, such as an InfoField exchange protocol defined in IEEE 802.3bp, among other protocols. Through the InfoField exchange, the transmitter may notify the link partner on the initial state and exact starting time of the data scrambler 218. Further, once activated and synchronized, both the transmit data scrambler and the receive data de-scrambler may run continuously, thus maintaining synchronization without requiring transmission of periodic sync-words afterwards, as long as the clock timing remain locked between the two PHY'"'"'s. Accordingly, the de-scrambler at the receiver'"'"'s PHY circuitry may not be affected by bit errors, as long as clock timing remains locked. The de-scrambled bits output by the data de-scrambler 274 may be forwarded to the data decoder 277. The de-scrambled bits may include the data bits, the OAM bits, and the corresponding parity check bits.
The data decoder 277 may be a decoder corresponding to the data encoder 215. The data decoder 277, for example, may be a RS decoder corresponding to the RS encoder in the transmitter 201. The RS decoder may be setup with setting values similar to those in the RS encoder to be compliant with the same standard as the transmitter 201. Accordingly, the RS decoder may group the de-scrambled bits into FEC frames of the predetermined length of the FEC frame. For example, the RS decoder may divide the 4050 de-scrambled bits into 450 9-bit FEC frames that include 406 RSD symbols and 44 RSC symbols. The RS decoder may subsequently convert the FEC frames into PCS blocks of the predetermined length. For example, corresponding to the transmitter 201 example above, the RS decoder may convert the decoded 406 9-bit RS symbols into 45 81-bit PCS blocks and 9 OAM bits. The PCS blocks may be forwarded to the PCS de-framer 280. The data decoder 277 may forward the OAM bits decoded from the de-scrambled bits to the circuitry that handles OAM standards or protocols.
The PCS de-framer 280 may be circuitry that converts the PCS blocks into MAC layer data. For example, the PCS de-framer may, based on header information in the PCS block, convert the PCS block data into MAC layer data. In the above example, the PCS de-framer may output 10 8-bit words for each 81-bit PCS block. The PCS de-framer output may be transmitted via the media independent interface 205 for further processing by the MAC circuitry. For example, the data may be forwarded to an automobile component for further processing.
The methods, devices, processing, and logic described above may be implemented in many different ways and in many different combinations of hardware and software. For example, all or parts of the implementations may be circuitry that includes an instruction processor, such as a Central Processing Unit (CPU), microcontroller, or a microprocessor; an Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or Field Programmable Gate Array (FPGA); or circuitry that includes discrete logic or other circuit components, including analog circuit components, digital circuit components or both; or any combination thereof. The circuitry may include discrete interconnected hardware components and/or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a Multiple Chip Module (MCM) of multiple integrated circuit dies in a common package, as examples.
The circuitry may further include or access instructions for execution by the circuitry. The instructions may be stored in a tangible storage medium that is other than a transitory signal, such as a flash memory, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM); or on a magnetic or optical disc, such as a Compact Disc Read Only Memory (CDROM), Hard Disk Drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and the instructions when executed by the circuitry in a device may cause the device to implement any of the processing described above or illustrated in the drawings.
The implementations may be distributed as circuitry among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library, such as a shared library (e.g., a Dynamic Link Library (DLL)). The DLL, for example, may store instructions that perform any of the processing described above or illustrated in the drawings, when executed by the circuitry.
Various implementations have been specifically described. However, many other implementations are also possible.