Accessing data via different clocks
First Claim
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1. A method comprising:
- accessing data of a first domain that is driven by a first clock via a second clock; and
synchronizing the first clock and the second clock to produce a defined phase-relation between the first clock and the second clock when accessing the data of the first domain, wherein the first domain comprises a processing unit driven by the first clock and a memory that is accessible to the processing unit, a second domain comprises a second processing unit driven by the second clock, and the second processing unit is arranged to access the memory of the first domain.
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Abstract
An example relates to a method for accessing data of a first domain that is driven by a first clock via a second clock, comprising at least one of the following: accessing the data of the first domain via the second clock during a time when the first clock is in a first logical state. An edge indicating a transition from a second logical state to the first logical is used to access data via the first clock, or accessing the data of the first domain via the second clock at edges of the first clock that are synchronized with edges of the second clock.
119 Citations
22 Claims
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1. A method comprising:
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accessing data of a first domain that is driven by a first clock via a second clock; and synchronizing the first clock and the second clock to produce a defined phase-relation between the first clock and the second clock when accessing the data of the first domain, wherein the first domain comprises a processing unit driven by the first clock and a memory that is accessible to the processing unit, a second domain comprises a second processing unit driven by the second clock, and the second processing unit is arranged to access the memory of the first domain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A device comprising:
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a first domain comprising first clock circuit configured to generate a first clock signal and a memory configured to store data to be accessed; a second domain comprising a second clock circuit configured to generate a second clock signal and a second processing unit, the second processing unit coupled to the memory; and a synchronizer circuit coupled to the first clock circuit and the second clock circuit, the synchronizer circuit configured to synchronize the first clock signal and the second clock signal to have a defined phase-relation for accessing the data, wherein the first domain is a standby domain and the second domain is a core domain, wherein the second clock signal operates at a higher frequency than the first clock signal. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A device for accessing data that is driven by a first clock via a second clock, the device comprising:
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a first domain comprising the first clock and a memory for storing the data; a second domain comprising the second clock and a second processing unit; and means for setting the first clock and the second clock to a defined phase-relation for accessing the data, wherein the first clock is used for accessing the data of the first domain in case the second clock is switched off.
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Specification