Transceiver and clock generation module

• US 10,447,466 B2
• Filed: 12/21/2018
• Issued: 10/15/2019
• Est. Priority Date: 01/18/2018
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hsu, Ying-Yu, Chuang, Chih-Lun, Kuo, Po-Chun
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US16/229,155
• Publication Number:
  US 20190222410A1
• Time in Patent Office: 298 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Abstract

A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

Claims

1. A transceiver, comprising:

a receiver, configured to receive a receiving-input-data and a receiving-input-strobe, wherein the receiving-input-data and the receiving-input-strobe have a receiving-input phase difference, and the receiver comprises;

a data-receiving circuit configured to delay the receiving-input-data and accordingly generate a receiving-delayed-data;

a strobe-receiving circuit, configured to delay the receiving-input-strobe and accordingly generate a receiving-delayed-strobe; and

a clock generation module, electrically connected to the receiver, comprising;

a calibration circuit, configured to selectively generate one of a first set of phase control signals comprising a strobe-phase-compensation signal and a second set of phase control signals comprising a data-phase-compensation signal; and

a phase-compensation module, comprising;

a data-phase-compensation circuit, electrically connected to the data-receiving circuit and the calibration circuit, configured to generate a receiving-path-data by delaying the receiving-delayed-data with a receiving-data compensation when the data-phase-compensation signal is generated; and

a strobe-phase-compensation circuit, electrically connected to the strobe-receiving circuit and the calibration circuit, configured to generate a receiving-path-strobe by delaying the receiving-delayed-strobe with a receiving-strobe compensation when the strobe-phase-compensation signal is generated,

wherein the receiving-path-data and the receiving-path-strobe have a receiving-path phase difference which is different from the receiving-input phase difference; and

a multi-phase signal generator, electrically connected to the calibration circuit, configured to generate a first shifted system-clock signal and a second shifted system-clock signal based on a system-clock signal, wherein a first shifted system-clock difference between the second shifted system-clock signal and the first shifted system-clock signal is equivalent to the receiving-path phase difference.

2. The transceiver according to claim 1, wherein the receiving-input-data and the receiving-input-strobe are edge-aligned, and the receiving-path-strobe is 90 degrees out of phase with the receiving-path-data.

3. The transceiver according to claim 1, wherein the multi-phase signal generator further generates a third shifted system-clock signal, and a second shifted system-clock difference between the third shifted system clock and the first shifted system-clock signal is equivalent to a third shifted system-clock difference between the second shifted system-clock signal and the third sifted system-clock signal, wherein

the first shifted system-clock difference is equivalent to a summation of the second shifted system-clock difference and the third shifted system-clock difference.

4. The transceiver according to claim 3, wherein the transceiver further comprises a transmitter and the clock generation module further comprises:

a divider, electrically connected to the multi-phase signal generator and the transmitter, configured to receive the first shifted system-clock signal and the third shifted system-clock signal, and accordingly generate a plurality of multi-phase memory-clock signals.

5. The transceiver according to claim 4, wherein cycle of the system-clock signal is equivalent to half of cycles of the plurality of multi-phase memory-clock signals.

6. The transceiver according to claim 1, wherein the multi-phase signal generator comprises:

a first phase-generation-path, configured to receive the system-clock signal and generate the first shifted system-clock signal according to a first phase-configuration signal from the calibration circuit;

a second phase-generation-path, comprising;

a first sub-circuit, electrically connected to a symmetric terminal and configured to receive the system-clock signal and selectively receive a first-second phase-configuration signal from the calibration circuit; and

a second sub-circuit, electrically connected to the symmetric terminal, configured to selectively receive a second-second phase-configuration signal from the calibration circuit and generate the second shifted system-clock signal, wherein the first sub-circuit and the second sub-circuit are symmetric; and

a third phase-generation-path, electrically connected to the symmetric terminal, configured to selectively receive a third phase-configuration signal from the calibration circuit and generate the third system-clock signal,

wherein the first set of phase control signals further comprises the first-second phase-configuration signal and the second-second phase-configuration signal, and the second set of phase control signals further comprises the first phase-configuration signal and the third phase-configuration signal.

7. The transceiver according to claim 6, wherein

the calibration circuit generates the first set of phase control signals when phase difference between the receiving-delayed-strobe, and the receiving-delayed-data is satisfied with a first predefined comparison condition;

and

the calibration circuit generates the second set of phase control signals when the phase difference between the receiving-delayed-strobe, and the receiving-delayed-data is satisfied with a second predefined comparison condition,

wherein the receiving-delayed-data is corresponding to the first shifted system-clock signal, and the receiving-delayed-strobe is corresponding to the second shifted system-clock signal.

8. The transceiver according to claim 7, wherein

the first predefined comparison condition is satisfied when the phase difference between the second shifted system-clock signal and the first shifted system-clock signal is greater than a default sampling-phase;

and

the second predefined comparison condition is satisfied when the phase difference between the second shifted system-clock signal and the first shifted system-clock signal is less than the default sampling-phase.

9. The transceiver according to claim 8, wherein the default sampling-phase is equivalent to half of cycle of the system-clock signal.

10. The transceiver according to claim 6, wherein the first phase-generation-path comprises:

a first controllable phase-delay circuit, configured to delay the system-clock signal with a first controllable phase-delay to generate the first shifted system-clock signal when the first phase-configuration signal is generated.

11. The transceiver according to claim 10, wherein

the first sub-circuit comprises:

a second controllable phase-delay circuit corresponding to a second controllable phase-delay; and

a first semi-sampling-delay matching circuit corresponding to a first semi-default sampling-phase; and

the second sub-circuit comprises;

a third controllable phase-delay circuit corresponding to a third controllable phase-delay; and

a second semi-sampling-delay matching circuit corresponding to a second semi-default sampling-phase,

wherein the second controllable phase-delay is equivalent to the third controllable phase-delay, and the first semi-default sampling-phase is equivalent to the second semi-default sampling-phase.

12. The transceiver according to claim 11, wherein summation of the first semi-default sampling-phase and the second semi-default sampling-phase is equivalent to half of cycle of the system-clock signal.

13. The transceiver according to claim 11, wherein

the first sub-circuit is configured to delay the system-clock signal with the second controllable phase-delay and the first semi-default sampling-phase and generate a signal at the symmetric terminal when the first-second phase-configuration signal is generated;

and

the second sub-circuit is configured to delay the signal at the symmetric terminal with the third controllable phase-delay and the second semi-default sampling-phase to generate the second shifted system-clock signal when the second-second phase-configuration signal is generated.

14. The transceiver according to claim 13, wherein the third phase-generation-path comprises:

a fourth controllable phase-delay circuit, configured to delay the signal at the symmetric terminal with a fourth controllable phase-delay to generate the third shifted system-clock signal when the third phase-configuration signal is generated.

15. The transceiver according to claim 14, wherein the third phase-generation-path utilizes the signal at the symmetric terminal as the third shifted system-clock signal when the third phase-configuration signal is not generated.

16. The transceiver according to claim 14, wherein

the first controllable phase-delay circuit and the fourth phase delay circuit are disabled when the first predefined comparison condition is unsatisfied;

and

the second controllable phase-delay circuit and the third phase delay circuit are disabled when the second predefined comparison condition is unsatisfied.

17. The transceiver according to claim 6, wherein the calibration circuit comprises:

a phase detector, electrically connected to the first phase-generation-path and the second phase-generation-path, configured to receive the first shifted system-clock signal and the second shifted system-clock signal and generate a phase comparison signal according to comparison of phases of the first shifted system-clock signal and the second shifted system-clock signal; and

a delay control circuit, electrically connected to the phase detector, configured to generate the first set of phase control signals and the second set of phase control signals according to the phase comparison signal.

18. The transceiver according to claim 1, wherein the multi-phase signal generator receives the system-clock signal from a phase-locked loop (hereinafter, PLL) circuit.

19. A clock generation module, electrically connected to a receiver, wherein the receiver receives a receiving-input-data and a receiving-input-strobe, wherein the receiving-input-data and the receiving-input-strobe have a receiving-input phase difference, the receiving-input-data is delayed to generate a receiving-delayed-data, and the receiving-input-strobe is delayed to generate a receiving-delayed-strobe, and the clock generation module comprises:

a calibration circuit, configured to selectively generate one of a first set of phase control signals comprising a strobe-phase-compensation signal and a second set of phase control signals comprising a data-phase-compensation signal; and

a phase-compensation module, comprising;

a data-phase-compensation circuit, electrically connected to the receiver, configured to generate a receiving-path-data by delaying the receiving-delayed-data with a receiving-data compensation when the data-phase-compensation signal is generated; and

a strobe-phase-compensation circuit, electrically connected to the strobe-receiving circuit and the calibration circuit, configured to generate a receiving-path-strobe by delaying the receiving-delayed-strobe with a receiving-strobe compensation when the strobe-phase-compensation signal is generated,

wherein the receiving-path-data and the receiving-path-strobe have a receiving-path phase difference which is different from the receiving-input phase difference; and

a multi-phase signal generator, electrically connected to the calibration circuit, configured to generate a first shifted system-clock signal and a second shifted system-clock signal based on a system-clock signal, wherein a first shifted system-clock difference between the second shifted system-clock signal and the first shifted system-clock signal is equivalent to the receiving-path phase difference.