Low supply linear equalizer with programmable peaking gain

• US 10,447,507 B1
• Filed: 10/26/2018
• Issued: 10/15/2019
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Zhang, Xu, Jung, Soon-Gil, Yazdi, Ahmad
• Primary Examiner(s): Puente, Eva Y
• Application Number:
  US16/172,591
• Time in Patent Office: 354 Days
• Field of Search: 375232, 375229, 327559, 327563
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/45458 the CSC comprising one or more capacitors
• CPC Class Codes: H03F 2203/45464 the CSC comprising one or more coils
• CPC Class Codes: H03F 2203/45496 the CSC comprising one or more extra resistors
• CPC Class Codes: H03F 2203/45498 the CSC comprising only resistors
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03G 5/28 having semiconductor devices
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03267 with decision feedback equalisers
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

Claims

1. A linear equalizer, the linear equalizer comprising:

sets of transistors connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer;

a resistor connected to a supply voltage, to the at least one output terminal, and to the sets of transistors; and

first and second impedance elements connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage, wherein a peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

2. The linear equalizer of claim 1, wherein each set of transistors of the sets of transistors have the same transconductance, and wherein gate terminals or base terminals of transistors in each set of transistors are connected together.

3. The linear equalizer of claim 2, wherein the peaking gain of the linear equalizer is programmable by adjusting the DC component of the at least one input signal such that the transconductance of at least one set of transistors of the sets of transistors is changed.

4. The linear equalizer of claim 1, wherein each transistor of the sets of transistors is a bipolar junction transistor (BJT), and wherein the first and second impedance elements are connected between the emitter terminals of the sets of transistors and the at least one fixed voltage.

5. The linear equalizer of claim 4, wherein the at least one input signal is applied to base terminals of the sets of transistors.

6. The linear equalizer of claim 1, wherein each transistor of the sets of transistors is a field-effect transistor (FET), and wherein the first and second impedance elements are connected between the source terminals of the sets of transistors and the at least one fixed voltage.

7. The linear equalizer of claim 6, wherein the at least one input signal is applied to gate terminals of the sets of transistors.

8. The linear equalizer of claim 1, wherein the first impedance element comprises a second resistor, and wherein the second impedance element comprises a third resistor, an inductor, and a capacitor.

9. The linear equalizer of claim 8, wherein the third resistor is connected in parallel with the inductor and the capacitor.

10. The linear equalizer of claim 9, wherein the at least one fixed voltage is physical ground or alternating current (AC) ground.

11. A linear equalizer system, wherein the linear equalizer system comprises the linear equalizer of claim 1 and a DC bias generator configured to generate the DC component of the at least one input signal.

12. The linear equalizer system of claim 11, wherein the DC bias generator comprises a plurality of adjustable current sources whose current levels are adjusted in order to change the DC component of the at least one input signal.

13. A linear equalizer, the linear equalizer comprising:

a first set of transistors and a second set of transistors connected between two input terminals of the linear equalizer and an output terminal of the linear equalizer, wherein the first set of transistors has a first transconductance, and wherein the second set of transistors has a second transconductance;

a resistor connected to a supply voltage, to the output terminal, and to the first and second sets of transistors; and

first and second impedance elements connected between emitter terminals or source terminals of the first and second sets of transistors and at least one fixed voltage, wherein a peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of an input signal that is received at the two input terminals and that is applied to the first and second sets of transistors.

14. The linear equalizer of claim 13, wherein the first transconductance is different from the second transconductance, and wherein gate terminals or base terminals of transistors in each of the first and second sets of transistors are connected together.

15. The linear equalizer of claim 14, wherein the peaking gain of the linear equalizer is programmable by adjusting the DC component of the at least one input signal such that the first transconductance of the first set of transistors or the second transconductance of the second set of transistors is changed.

16. The linear equalizer of claim 13, wherein each transistor of the first and second sets of transistors is a bipolar junction transistor (BJT), wherein the first and second impedance elements are connected between the emitter terminals of the first and second sets of transistors and the at least one fixed voltage, and wherein the at least one input signal is applied to base terminals of the first and second sets of transistors.

17. The linear equalizer of claim 13, wherein each transistor of the first and second sets of transistors is a field-effect transistor (FET), wherein the first and second impedance elements are connected between the source terminals of the first and second sets of transistors and the at least one fixed voltage, and wherein the at least one input signal is applied to gate terminals of the first and second sets of transistors.

18. The linear equalizer of claim 13, wherein the first impedance element comprises a second resistor, wherein the second impedance element comprises a third resistor, an inductor, and a capacitor, and wherein the third resistor is connected in parallel with the inductor and the capacitor between the emitter terminals or the source terminals of the sets of transistors and the at least one fixed voltage.

19. A linear equalizer system, wherein the linear equalizer system comprises the linear equalizer of claim 13 and a DC bias generator, which comprises a plurality of adjustable current sources whose current levels are adjusted in order to change the DC component of the at least one input signal.

20. A differential linear equalizer, the differential linear equalizer comprising:

first, second, third, and fourth sets of transistors connected between four input terminals of the differential linear equalizer and two output terminals of the differential linear equalizer, wherein the first and third sets of transistors have a first transconductance, and wherein the second and fourth sets of transistors have a second transconductance;

two resistors connected to a supply voltage, to the two output terminals, and to the first, second, third, and fourth sets of transistors; and

first and second impedance elements connected between emitter terminals or source terminals of the first, second, third, and fourth sets of transistors and at least one fixed voltage, wherein a peaking gain of the differential linear equalizer is programmable by adjusting a direct current (DC) component of the two input signals that are received at the fourth input terminals and that are applied to the first, second, third, and fourth sets of transistors.