Precompensator-based quantization for clock recovery

• US 10,447,509 B1
• Filed: 08/23/2018
• Issued: 10/15/2019
• Est. Priority Date: 08/23/2018
• Status: Active Grant

• Current Assignee: Credo Technology Group Limited (Credo Technology Group Holding Ltd.)
• Original Assignee: Credo Technology Group Limited (Credo Technology Group Holding Ltd.)
• Inventors: Cai, Fang, Sun, Junqing, Qian, Haoli
• Primary Examiner(s): Wang, Ted M
• Application Number:
  US16/110,594
• Time in Patent Office: 418 Days
• CPC Class Codes: H04B 14/023 using pulse amplitude modulation
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence

Abstract

Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel. One illustrative method embodiment includes: (a) obtaining a receive signal having a sequence of symbols from a symbol set, the receive signal exhibiting trailing intersymbol interference; (b) operating on the receive signal with a precompensation unit having a set of comparators to produce, for each sampling instant, a set of comparator results representing a quantized receive signal value, the set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference; (c) deriving a symbol decision from each set of comparator results; (d) combining the symbol decisions with said quantized receive signal values to determine an estimated timing error for each sampling instant; and (e) filtering the estimated timing errors to generate a sampling clock.

Claims

1. A method of providing high speed equalization, the method comprising:

obtaining a receive signal having a sequence of symbols from a symbol set, the receive signal having trailing intersymbol interference;

operating on the receive signal with a precompensation unit having a set of comparators to produce, for each sampling instant, a set of comparator results representing a quantized receive signal value, the set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference;

deriving a symbol decision from each set of comparator results;

combining the symbol decisions with said quantized receive signal values to determine an estimated timing error for each sampling instant; and

filtering the estimated timing errors to generate a sampling clock.

2. The method of claim 1, wherein said deriving includes using the comparator results to form a set of tentative decisions for each sampling instant and, based on one or more symbol decisions preceding that sampling instant, selecting a symbol decision from the set of tentative decisions.

3. The method of claim 1, wherein the set of threshold values is nonuniformly spaced and yields a nonuniformly spaced set of possible values for the quantized receive signal.

4. The method of claim 3, wherein the set of possible values includes values midway between each pair of neighboring threshold values, and further includes a maximum value greater than the maximum threshold value by a given amount and a minimum value less than the minimum threshold value by the given amount.

5. The method of claim 4, wherein the given amount minimizes expected quantization error.

6. The method of claim 4, further comprising adapting the threshold values based to improve compensation of the trailing intersymbol interference.

7. The method of claim 3, wherein the symbol set includes more than two symbols.

8. The method of claim 3, wherein said combining includes:

scaling a quantized receive signal value for a given sampling instant by a polarity or signed value of a symbol decision for a preceding sampling instant to obtain a first term;

scaling a quantized receive signal value for the preceding sampling instant by a polarity or signed value of a symbol decision for the given sampling instant to obtain a second term; and

taking a difference between the first and second terms as the estimated timing error for the given sampling instant.

9. The method of claim 3, wherein the combining includes:

determining a target signal level for a given sampling instant based at least in part on a symbol decision for the given instant; and

taking a difference between the target signal level and a quantized receive signal value for the given sampling instant to obtain a discrepancy for the given instant.

10. The method of claim 9, wherein the combining further includes:

scaling the discrepancy for the given sampling instant by a polarity or signed value of a symbol decision for a preceding sampling instant to obtain a first term;

scaling a discrepancy for the preceding sampling instant by a polarity or signed value of a symbol decision for the given sampling instant to obtain a second term; and

taking a difference between the first and second terms as the estimated timing error for the given sampling instant.

11. A channel interface module that comprises a receiver having:

a front end filter that produces a filtered receive signal having a sequence of symbols from a symbol set, the filtered receive signal having trailing intersymbol interference;

a precompensation unit that operates on the filtered receive signal with a set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference, the set of comparators producing, for each sampling instant, a set of comparator results representing a quantized receive signal value;

one or more selection elements that derive a symbol decision from each set of comparator results;

a clock recovery module that combines the symbol decisions with said quantized receive signal values to generate a sampling clock.

12. The module of claim 11, wherein the comparator results are organized as a set of tentative decisions for each sampling instant, and wherein each of the one or more selection elements selects a symbol decision from a corresponding set of tentative decisions.

13. The module of claim 11, wherein the set of threshold values is nonuniformly spaced and yields a nonuniformly spaced set of possible values for the quantized receive signal.

14. The module of claim 13, wherein the set of possible values includes values midway between each pair of neighboring threshold values, and further includes a maximum value greater than the maximum threshold value by a given amount and a minimum value less than the minimum threshold value by the given amount.

15. The module of claim 14, wherein the given amount minimizes expected quantization error.

16. The module of claim 14, further comprising adaptation units that adapt the threshold values based to improve compensation of the trailing intersymbol interference.

17. The module of claim 13, wherein said clock recovery module includes:

a first scaler that scales a quantized receive signal value for a given sampling instant by a polarity or signed value of a symbol decision for a preceding sampling instant to obtain a first term;

a second scaler that scales a quantized receive signal value for the preceding sampling instant by a polarity or signed value of a symbol decision for the given sampling instant to obtain a second term; and

a combiner that determines a difference between the first and second terms and produces the difference as the estimated timing error for the given sampling instant.

18. The module of claim 13, wherein said clock recovery module includes:

a targeting element that produces a target signal level for a given sampling instant based at least in part on a symbol decision for the given instant; and

a first combiner that takes a difference between the target signal level and a quantized receive signal value for the given sampling instant to obtain a discrepancy for the given instant.

19. The module of claim 18, wherein the clock recovery module further includes:

a first scaler that scales the discrepancy for the given sampling instant by a polarity or signed value of a symbol decision for a preceding sampling instant to obtain a first term;

a second scaler that scales the discrepancy for the preceding sampling instant by a polarity or signed value of a symbol decision for the given sampling instant to obtain a second term; and

a second combiner that determines a difference between the first and second terms and produces the difference as the estimated timing error for the given sampling instant.

20. The module of claim 19, wherein the clock recovery module further includes:

a filter that filters the estimated timing errors to produce a control signal; and

a voltage controlled oscillator that produces the sampling clock in response to the control signal.

21. The module of claim 13, wherein said clock recovery module includes:

a targeting element that produces a target signal level for a given sampling instant based at least in part on a symbol decision for the given instant;

a first scaler that scales the quantized receive signal value for the given sampling instant by a polarity or signed value of a target signal level for a preceding sampling instant to obtain a first term;

a second scaler that scales the quantized receive signal value for the preceding sampling instant by a polarity or signed value of a target signal level for the given sampling instant to obtain a second term; and

a combiner that determines a difference between the first and second terms and produces the difference as the estimated timing error for the given sampling instant.