Memory network and system including the same

• US 10,447,584 B2
• Filed: 12/21/2015
• Issued: 10/15/2019
• Est. Priority Date: 09/15/2015
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Gwangsun, Kim, John Dongjun, Kwon, Yong-Kee
• Primary Examiner(s): Sain, Gautam
• Application Number:
  US14/976,578
• Publication Number:
  US 20170075578A1
• Time in Patent Office: 1,394 Days
• Field of Search: 711154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: H04L 45/40 Wormhole routing

Abstract

A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Claims

1. A memory network comprising:

a plurality of memory devices arranged in a matrix as a plurality of rows provided along a first direction of the matrix and a plurality of columns provided along a second direction of the matrix that is different from the first direction, the plurality of rows including a first row of memory devices, a second row of memory devices, and a third row of memory devices, the plurality of columns including a first column of memory devices including a first memory device of the plurality of memory devices, a second memory device of the plurality of memory devices, and a third memory device of the plurality of memory devices, such that the first memory device is comprised in the first row, the second memory device is comprised in the second row, and the third memory device is comprised in the third row;

a plurality of memory channels including a first memory channel directly connecting the first memory device and the second memory device of the first column and a second memory channel directly connecting the first memory device and the third memory device of the first column, the second memory device being disposed between the first memory device and the third memory device, wherein the memory devices in the first column are not directly connected to memory devices in any other column of the plurality of columns; and

a plurality of processor channels including a first processor channel connecting each of the memory devices in the first row to only a first processor of a plurality of processors, a second processor channel connecting each of the memory devices in the second row to only a second processor of the plurality of processors, and a third processor channel connecting each of the memory devices in the third row to only a third processor of the plurality of processors,

wherein the first processor channel does not directly connect to any of the memory devices in the second row and the third row, the second processor channel does not directly connect to any of the memory devices in the first row and the third row, and the third processor channel does not directly connect to any of the memory devices in the first row and the second row, and

wherein the memory devices in the first row are not directly connected to other memory devices in the first row, the memory devices in the second row are not directly connected to other memory devices in the second row, and the memory devices in the third row are not directly connected to other memory devices in the third row.

2. The memory network of claim 1, wherein each of the plurality of processors is a CPU or a GPU.

3. The memory network of claim 1, wherein each of the plurality of memory devices comprises a pass-thru path configured to directly output an input signal, and the pass-thru path is configured to connect two neighboring memory devices in a column among the plurality of columns or to connect any of memory devices in the column and a corresponding processor of the plurality of processors.

4. The memory network of claim 3, wherein in a first routing path including the pass-thru path, a first data packet associated with the first processor has a higher routing priority than a second data packet associated with the second processor, wherein the first processor is a CPU and the second processor is a GPU.

5. A system comprising:

a plurality of processors;

a plurality of memory devices arranged in a matrix as a plurality of rows provided along a first direction of the matrix and a plurality of columns provided along a second direction of the matrix that is different from the first direction, the plurality of rows including a first row of memory devices, a second row of memory devices, and a third row of memory devices, the plurality of columns including a first column of memory devices including a first memory device of the plurality of memory devices, a second memory device of the plurality of memory devices, and a third memory device of the plurality of memory devices, such that the first memory device is comprised in the first row, the second memory device is comprised in the second row, and the third memory device is comprised in the third row;

a plurality of memory channels including a first memory channel directly connecting the first memory device and the second memory device of the first column and a second memory channel directly connecting the first memory device and the third memory device of the first column, the second memory device being disposed between the first memory device and the third memory device, wherein the memory devices in the first column are not directly connected to the memory devices in any other column of the plurality of columns; and

a plurality of processor channels including a first processor channel connecting each of the memory devices in the first row to only a first processor, a second processor channel connecting each of the memory devices in the second row to only a second processor, and a third processor channel connecting each of the memory devices in the third row to only a third processor,

wherein the first processor channel does not directly connect to any of the memory devices in the second row and the third row, the second processor channel does not directly connect to any of the memory devices in the first row and the third row, and the third processor channel does not directly connect to any of the memory devices in the first row and the second row, and

wherein the memory devices in the first row are not directly connected to other memory devices in the first row, the memory devices in the second row are not directly connected to other memory devices in the second row, and the memory devices in the third row are not directly connected to other memory devices in the third row.

6. The system of claim 5, wherein each of the plurality of processors is a CPU or a GPU.

7. The system of claim 5, wherein the first processor connected to the memory devices in the first row is a CPU, and the second processor connected to the memory devices in the second row is a GPU.

8. The system of claim 5, wherein each of the plurality of memory devices comprises a pass-thru path configured to directly output an input signal, and the pass-thru path is configured to connect two neighboring memory devices in a column among the plurality of columns or to connect any of memory devices in the column and a corresponding processor.

9. The system of claim 8, wherein in a first routing path including the pass-thru path, a first data packet associated with the first processor has a higher routing priority than a second data packet associated with the second processor, wherein the first processor is a CPU and the second processor is a GPU.