Digital signal receiver and method for controlling signal processing in such digital signal receiver

• US 10,448,337 B2
• Filed: 03/23/2017
• Issued: 10/15/2019
• Est. Priority Date: 03/23/2016
• Status: Active Grant

• Current Assignee: Montage LZ Semiconductor (shanghai) Co., ltd., Montage Lz Technologies (Chengdu) Co.Ltd.
• Original Assignee: Montage LZ Semiconductor (shanghai) Co., ltd.
• Inventors: Si, Xiaomin, Chen, Yu, Nie, Yuanfei, Lu, Zhen, Ren, Qinghai, Lu, Ruifeng
• Primary Examiner(s): Lamarre, Guy J
• Application Number:
  US15/466,880
• Publication Number:
  US 20170280396A1
• Time in Patent Office: 936 Days
• CPC Class Codes: H04L 1/0051 Stopping criteria
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04W 52/0261 managing power supply demand, e.g. depending on battery level
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.

Claims

1. A method for controlling signal processing in a digital signal receiver, wherein the digital signal receiver comprises an iterative signal processing module processing its input signal using an iterative processing algorithm and receiving a supply voltage adjustable by a voltage regulator within a preset supply voltage range allowing normal operation of the iterative signal processing module, and the method comprises:

detecting, for the iterative signal processing module, signal quality of its input signal and a parameter indicating power consumption of the iterative signal processing module;

adjusting the supply voltage of the iterative signal processing module, based on the detected parameter indicating the power consumption of the iterative signal processing module, so as to maintain the supply voltage within the preset supply voltage range; and

adjusting a maximum iteration number of signal processing for the iterative signal processing module based on the detected signal quality of its input signal, when the supply voltage of the iterative signal processing module is maintained within the preset supply voltage range.

2. The method according to claim 1, wherein the step of adjusting the maximum iteration number further comprises:

increasing the maximum iteration number of signal processing for the iterative signal processing module to improve its signal processing performance, or decreasing the maximum iteration number of signal processing for the iterative signal processing module to reduce its power consumption.

3. The method according to claim 1, wherein the parameter indicating the power consumption of the iteration signal processing module comprises at least one of the supply voltage and temperature of the iterative signal processing module.

4. The method according to claim 1, wherein the iterative signal processing is a forward error correction (FEC) decoder using an iterative processing algorithm, and the detecting step comprises detecting a signal-to-noise ratio (SNR) or bit error rate (BER) of the input signal of the FEC decoder as the signal quality of the input signal of the FEC decoder;

and wherein the step of adjusting the maximum iteration number of signal processing further comprises;

adjusting the maximum iteration number of signal processing of the FEC decoder based on the SNR or BER of the input signal of the FEC decoder, such that a value of the maximum iteration number of signal processing when the SNR or BER is in a no convergence region is smaller than a value of the max iteration number when the SNR or BER is in a waterfall region or an error floor region.

5. The method according to claim 4, wherein the FEC decoder is a low density parity check (LDPC) decoder, and the iterative processing algorithm used by the LDPC decoder is iterative LDPC decoding algorithm.

6. The method according to claim 4, wherein the FEC decoder is a Turbo code decoder, and the iterative processing algorithm used by the Turbo code decoder is iterative Turbo code decoding algorithm.

7. The method according to claim 4, wherein when the BER of the input signal of the FEC decoder is detected as the signal quality of the input signal of the FEC decoder, the detection of the BER is performed after a preset number of times of iteration in iterative processing.

8. The method according to claim 4, wherein the method further comprises:

decreasing the supply voltage of the FEC decoder and maintaining it within the preset supply voltage range, when the SNR or BER of the input signal of the FEC decoder is in the no convergence region.

9. The method according to claim 4, wherein the step of adjusting the maximum iteration number of signal processing further comprises:

adjusting the maximum iteration number of signal processing of the FEC decoder, such that a value of the maximum iteration number of signal processing when the SNR or BER of the input signal of the FEC decoder is in an error floor region is smaller than a value of the maximum iteration number of signal processing when the SNR or BER of the input signal of the FEC decoder is in a waterfall region.

10. The method according to claim 9, wherein the value of the maximum iteration number of signal processing of the FEC decoder when the SNR or BER of the input signal of the FEC decoder is in the error floor region is 50% to 90% of the value of the maximum iteration number of signal processing of the FEC decoder when the SNR or BER of the input signal of the FEC decoder is in the waterfall region.

11. The method according to claim 1, wherein the iterative signal processing module is a channel equalizer using an iteration processing algorithm, and the detecting step further comprises detecting a SNR of the input signal of the channel equalizer as the signal quality of the input signal of the channel equalizer;

and the step of adjusting the maximum iteration number of signal processing further comprises;

decreasing the maximum iteration number of signal processing of the channel equalizer when the SNR of the input signal of the channel equalizer increases;

or

setting the maximum iteration number of signal processing of the channel equalizer as a high SNR iteration number when the SNR of the input signal of the channel equalizer is higher than a preset threshold, and setting the maximum iteration number of signal processing as a low SNR iteration number when the SNR of the input signal of the channel equalizer is equal to or lower than the preset threshold, wherein the low SNR iteration number is larger than the high SNR iteration number.

12. A digital signal receiver, comprising:

an iterative decoder, configured to decode its input signal using an iterative decoding algorithm;

a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder;

a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder;

a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range which allows normal operation of the iterative decoder, based on the detected parameter indicating the power consumption of the iterative decoder; and

an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.

13. The digital signal receiver according to claim 12, wherein the iteration controller is further configured to increase the maximum iteration number of decoding of the iterative decoder to improve its signal processing performance, or decrease the maximum iteration number to reduce its power consumption.

14. The digital signal receiver according to claim 12, wherein the parameter indicating the power consumption of the iteration decoder comprises at least one of the supply voltage and temperature of the iterative decoder.

15. The digital signal receiver according to claim 12, wherein the iterative decoder is a FEC decoder, and the signal quality of the input signal of the FEC decoder comprises a SNR or BER of the input signal of the FEC decoder;

and wherein the iteration controller is further configured to adjust the maximum iteration number of decoding, such that a value of the maximum iteration number of decoding when the SNR or BER of the input signal of the iterative decoder is in a no convergence region is smaller than a value of the maximum iteration number of decoding when the SNR or BER of the input signal of the iterative decoder is in a waterfall region or an error floor region, and the value of the maximum iteration number of decoding when the SNR or BER is in the error floor region is smaller than the value of the maximum iteration number of decoding when the SNR or BER is in the waterfall region.

16. The digital signal receiver according to claim 15, wherein the iterative decoder is a LDPC decoder, and the iterative decoding algorithm used by the LDPC decoder is iterative LDPC decoding algorithm.

17. The digital signal receiver according to claim 15, wherein the iterative decoder is a Turbo decoder, and the iterative decoding algorithm used by the Turbo decoder is iterative Turbo decoding algorithm.

18. The digital signal receiver according to claim 12, wherein the digital signal receiver further comprises:

an iterative channel equalizer, configured to equalize its input signal using an iterative equalization algorithm;

and wherein the signal quality detector is further configured to detect signal quality of the input signal of the iterative channel equalizer;

and wherein the iteration controller is further configured to adjust the maximum iteration number of equalization processing based on the signal quality of the input signal of the iterative channel equalizer.

19. The digital signal receiver according to claim 18, wherein the signal quality detector is configured to detect a SNR of the input signal of the iterative channel equalizer as the signal quality of the input signal of the iterative channel equalizer;

and wherein the iteration controller is further configured to decrease the maximum iteration number of equalization processing when the SNR of the input signal of the iterative channel equalizer increases.