Encapsulated microelectromechanical structure

• US 10,450,190 B2
• Filed: 08/21/2018
• Issued: 10/22/2019
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: SiTime Corporation (Megachips Corporation)
• Original Assignee: SiTime Corporation (Megachips Corporation)
• Inventors: Partridge, Aaron, Lutz, Markus, Gupta, Pavan
• Primary Examiner(s): Fourson, III, George R
• Application Number:
  US16/106,649
• Publication Number:
  US 20190055121A1
• Time in Patent Office: 427 Days
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/0035 for maintaining a controlled atmosphere inside of the chamber containing the MEMS
• CPC Class Codes: B81B 7/0058 for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00277 for maintaining a controlled atmosphere inside of the cavity containing the MEMS
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/0171 Doping materials
• CPC Class Codes: B81C 2203/031 Anodic bondings
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/037 Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036
• CPC Class Codes: B81C 2203/038 Bonding techniques not provided for in B81C2203/031 - B81C2203/037
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10N 30/306 Cantilevers

Abstract

In a MEMS device, an oxide layer is disposed between first and second semiconductor layers and MEMS resonator is formed within a cavity in the first semiconductor layer. A first electrically conductive feature functionally coupled to the MEMS resonator is exposed at a surface of the first semiconductor layer, and an insulating region is exposed at the surface of the first semiconductor layer adjacent the first electrically conductive feature. A semiconductor cover layer is bonded to the surface of the first semiconductor layer to hermetically seal the MEMS resonator within the cavity. A second electrically conductive feature extends through the semiconductor cover layer to contact the first electrically conductive feature, and an isolation trench extends through the semiconductor cover layer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features.

Claims

1. A method of fabricating a microelectromechanical system (MEMS) device, the method comprising:

forming within a semiconductor layer of a semiconductor-on-insulator (SOI) wafer;

a cavity with a MEMS resonator therein,

a first electrically conductive feature functionally coupled to the MEMS resonator and exposed at a first surface of the semiconductor layer, and

an insulating region exposed at the first surface of the semiconductor layer adjacent the first electrically conductive feature;

bonding a semiconductor cover wafer to the first surface of the semiconductor layer of the SOI wafer to hermetically seal the MEMS resonator within the cavity; and

forming within the semiconductor cover wafer a second electrically conductive feature that extends through the semiconductor cover wafer to contact the first electrically conductive feature, including forming an isolation trench that extends through the semiconductor cover wafer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features from a bulk region of the semiconductor cover wafer.

2. The method of claim 1 further comprising fabricating complementary metal oxide semiconductor (CMOS) transistor circuitry within the semiconductor cover wafer.

3. The method of claim 1 wherein forming the second electrically conductive feature within the semiconductor cover wafer comprises impurity doping at least a portion of the semiconductor cover wafer to render electrical conductivity thereof.

4. The method of claim 3 wherein forming the isolation trench comprises forming a trench that surrounds the impurity-doped portion of the semiconductor cover wafer such that the impurity-doped portion of the semiconductor cover wafer is electrically isolated from a region of the semiconductor cover wafer that surrounds the isolation trench.

5. The method of claim 1 further comprising filling the isolation trench with non-conducting oxide.

6. The method of claim 1 wherein forming the insulating region exposed at the first surface of the semiconductor layer adjacent the first electrically conductive feature comprises forming an insulating region that surrounds the first-surface exposure of the first electrically conductive feature.

7. The method of claim 1 wherein the semiconductor layer of the SOI wafer comprises single crystalline silicon, and wherein forming the first electrically conductive feature comprises doping at least a portion of the single crystalline silicon with a first type of impurity to render electrical conductivity.

8. The method of claim 7 wherein forming the insulating region comprises doping a region of the single crystalline silicon with a second type of impurity to render the insulating region electrically non-conductive.

9. The method of claim 1 wherein forming the insulating region comprises impurity doping a first region of the semiconductor layer to render the first region electrically non-conductive, the first region surrounding the exposure of the first electrically conductive feature at the first surface of the semiconductor layer.

10. The method of claim 9 wherein:

the semiconductor layer of the SOI wafer comprises single crystalline silicon,

impurity doping the first region of the semiconductor layer comprises doping the single crystalline silicon with a first type of impurity that reduces electrical conductivity thereof, and

the single crystalline silicon doped with the first type of impurity separates the isolation trench from the cavity.

11. A microelectromechanical system (MEMS) device comprising:

an oxide layer disposed between first and second semiconductor layers, the first semiconductor layer having formed therein;

a cavity,

a MEMS resonator within the cavity,

a first electrically conductive feature functionally coupled to the MEMS resonator and exposed at a surface of the first semiconductor layer, and

an insulating region exposed at the surface of the first semiconductor layer adjacent the first electrically conductive feature;

a semiconductor cover layer bonded to the surface of the first semiconductor layer to hermetically seal the MEMS resonator within the cavity, the semiconductor cover layer having formed therein (i) a second electrically conductive feature that extends through the semiconductor cover layer to contact the first electrically conductive feature, and (ii) an isolation trench that extends through the semiconductor cover layer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features from a bulk region of the semiconductor cover layer.

12. The MEMS device of claim 11 further comprising complementary metal oxide semiconductor (CMOS) transistor circuitry within the semiconductor cover layer.

13. The MEMS device of claim 11 wherein the second electrically conductive feature within the semiconductor cover layer comprises a region of the semiconductor cover layer impurity doped to render electrical conductivity thereof.

14. The MEMS device of claim 13 wherein the isolation trench surrounds the impurity-doped region of the semiconductor cover layer such that the impurity-doped region of the semiconductor cover layer is electrically isolated from a region of the semiconductor cover layer that surrounds the isolation trench.

15. The MEMS device of claim 11 wherein the isolation trench is filled with non-conducting oxide.

16. The MEMS device of claim 11 wherein the insulating region surrounds the exposure of the first electrically conductive feature at the surface of the first semiconductor layer.

17. The MEMS device of claim 11 wherein the first semiconductor layer comprises single crystalline silicon, and wherein the first electrically conductive feature comprises a first region of the single crystalline silicon doped with a first type of impurity to render electrical conductivity.

18. The MEMS device of claim 17 wherein the insulating region comprises a second region of the single crystalline silicon with a second type of impurity to render the insulating region electrically non-conductive.

19. The MEMS device of claim 11 wherein the insulating region comprises a first region of the first semiconductor layer impurity doped to render the first region electrically non-conductive, the first region surrounding the exposure of the first electrically conductive feature at the surface of the first semiconductor layer.

20. The MEMS device of claim 19 wherein:

the first semiconductor layer comprises single crystalline silicon;

the first region of the first semiconductor layer comprises a region of the single crystalline silicon doped with a first type of impurity that reduces electrical conductivity of the single crystalline silicon; and

the region of the single crystalline silicon doped with the first type of impurity separates the isolation trench from the cavity.