CVD apparatus with multi-zone thickness control

• US 10,450,655 B2
• Filed: 10/27/2017
• Issued: 10/22/2019
• Est. Priority Date: 10/27/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fang, Chung-Wei, Chiu, Yi Hsun, Li, Cho-Han, Dai, Yao Fong
• Primary Examiner(s): McCall-Shepard, Sonya D.
• Application Number:
  US15/795,730
• Publication Number:
  US 20190127852A1
• Time in Patent Office: 725 Days
• CPC Class Codes: C23C 16/4412 Details relating to the exhausts, e.g. pumps, filters, scrubbers, particle traps
• CPC Class Codes: C23C 16/45502 Flow conditions in reaction chamber
• CPC Class Codes: C23C 16/45565 Shower nozzles
• CPC Class Codes: C23C 16/52 Controlling or regulating the coating process C23C16/45557, C23C16/279 take precedence
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14

Abstract

The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through with at least two different diameters or densities. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.

Claims

1. A method of chemical vapor deposition (CVD), comprising:

determining a CMP remove profile of a chemical-mechanical polishing (CMP) process;

guiding a process gas of a precursor material through a block plate, the block plate having a plurality of apertures with smaller density or smaller size dimensions in a central region than an edge region, wherein an uneven arrangement of the plurality of apertures corrects an uneven accumulation of the process gas;

guiding the process gas out from the block plate through a shower head, the shower head being spatially separated from the block plate and having multiple control zones where holes of the shower head are unevenly distributed to direct the process gas to have an uneven distribution from the multiple control zones;

depositing the precursor material onto a semiconductor substrate according to the determined CMP remove profile, such that the deposited precursor material has a thickness profile that matches the CMP remove profile; and

performing the CMP process to the precursor material to form a dielectric or metal layer with a planar surface.

2. The method of claim 1, wherein the precursor material is deposited onto the semiconductor substrate such that a thickness of the precursor material increases from a center region to a peripheral region of the semiconductor substrate.

3. The method of claim 1, wherein the precursor material is deposited in a plasma enhanced chemical vapor deposition (PECVD) apparatus.

4. The method of claim 1, wherein the precursor material is deposited onto the semiconductor substrate such that a thickness of the precursor material decreases from a center region to a peripheral region of the semiconductor substrate.

5. The method of claim 1, further comprising:

after performing the CMP process, performing a surface profile analysis to the semiconductor substrate and generating an alteration surface profile; and

depositing a precursor material onto a second semiconductor substrate such that the deposited precursor material has a thickness profile that matches the alteration surface profile.

6. The method of claim 1, wherein the precursor material is an oxide material and is formed by a plasma enhanced tetraethylorthosilicate (PETEOS) process.

7. The method of claim 1, wherein the multiple control zones have the same number of hole rings, and an outer control zone of the multiple control zones has holes with an average diameter about 4% to about 8% greater than that of an inner control zone abutting the outer control zone.

8. The method of claim 1, wherein the shower head is selected, or an hole arrangement of the shower head is adjusted according to the CMP remove profile.

9. The method of claim 2, wherein the thickness of the precursor material in the peripheral region of the semiconductor substrate is at least 3% greater than that of the center region.

10. The method of claim 2, wherein the thickness of the precursor material increases linearly from the center region to the peripheral region of the semiconductor substrate.

11. A method of forming a planar dielectric layer over a semiconductor substrate, comprising:

providing a CMP remove profile of a CMP process;

applying a process gas into a vacuum chamber from a gas import arranged near an upper region of the vacuum chamber;

guiding the process gas downstream the vacuum chamber through a shower head arranged under the gas import, where the process gas is redirected to be laterally unevenly distributed under the shower head;

depositing the process gas onto the semiconductor substrate arranged between the shower head and an exhaust port arranged near a bottom region of the vacuum chamber to form a dielectric material, such that the dielectric material has an uneven thickness profile from a center region to an edge region of the semiconductor substrate as a result of uneven distribution of the process gas; and

performing a chemical-mechanical polishing (CMP) process to the dielectric material such that the dielectric material is polished to form a dielectric layer with a substantially planar top surface;

wherein the uneven thickness profile of the dielectric material matches the CMP remove profile of the CMP process.

12. The method of claim 11, further comprising:

performing a surface profile analysis to the dielectric layer and generating an alteration surface profile;

replacing or adjusting the shower head within the vacuum chamber according to the alteration surface profile; and

placing a second semiconductor substrate to the vacuum chamber to deposit the dielectric material onto the second semiconductor substrate such that the dielectric material has a thickness profile matches the alteration surface profile.

13. The method of claim 11, wherein the dielectric material is deposited on the semiconductor substrate such that a thickness of the dielectric material increases from a center region to a peripheral region of the semiconductor substrate.

14. The method of claim 11,

wherein the shower head of the vacuum chamber is prepared to have at least three control zones defined from a center region to an edge region, wherein each of the control zones has a plurality of holes with an average diameter, wherein the average diameter monotonously increases or decreases from the center region to the edge region.

15. The method of claim 11, wherein the dielectric material is formed by a plasma enhanced chemical vapor deposition (PECVD) process.

16. The method of claim 11, wherein the uneven thickness profile of the dielectric material is controlled by adjusting a hole arrangement of the shower head of the vacuum chamber.

17. A method, comprising:

applying a process gas into a vacuum chamber from a gas import arranged near an upper region of the vacuum chamber;

guiding the process gas downstream the vacuum chamber through a shower head arranged under the gas import, where the process gas is redirected to be laterally unevenly distributed under the shower head, wherein a density of the process gas increases from a center region to a peripheral region of the vacuum chamber;

depositing the process gas onto a first semiconductor substrate arranged between the shower head and an exhaust port arranged near a bottom region of the vacuum chamber to form a precursor material with an uneven thickness profile as a result of uneven distribution of the process gas; and

performing a chemical-mechanical polishing (CMP) process to the uneven thickness profile to form a substantially planar top surface, wherein the uneven thickness profile matches a CMP remove profile of the CMP process;

wherein the shower head has multiple control zones each having a plurality of holes disposed through the shower head, and an outer control zone of the multiple control zones has holes with an average diameter about 4% to about 8% greater than that of an inner control zone abutting the outer control zone.

18. The method of claim 17, further comprising:

performing a surface profile analysis after the CMP process to generate an alteration surface profile;

replacing or adjusting the shower head within the vacuum chamber according to the alteration surface profile; and

depositing the precursor material on a second semiconductor substrate in the vacuum chamber such that the deposited precursor material has a thickness profile that matches the alteration surface profile.

19. The method of claim 17,

wherein the shower head of the vacuum chamber is prepared to have at least three control zones defined from a center region to an edge region, wherein each of the control zones has a plurality of holes with an average diameter, wherein the average diameter monotonously increases or decreases from the center region to the edge region.

20. The method of claim 17, wherein the thickness of the precursor material in the peripheral region of the first semiconductor substrate is at least 3% greater than that of the center region.