VMIN retention detector apparatus and method
First Claim
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1. An apparatus comprising:
- a combinational logic to provide a data on a data node;
a multiplexer coupled to the data node and one of a supply node or a ground node, the multiplexer having an output node;
a sequential logic having a data input, an output, and a clock input, wherein the output node of the multiplexer is coupled to the data input; and
a compare logic having a first input coupled to the data input, and a second input coupled to the output of the sequential logic, wherein the compare logic is to detect a Vmin threshold of the sequential logic during a test mode.
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Abstract
Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.
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Citations
20 Claims
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1. An apparatus comprising:
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a combinational logic to provide a data on a data node; a multiplexer coupled to the data node and one of a supply node or a ground node, the multiplexer having an output node; a sequential logic having a data input, an output, and a clock input, wherein the output node of the multiplexer is coupled to the data input; and a compare logic having a first input coupled to the data input, and a second input coupled to the output of the sequential logic, wherein the compare logic is to detect a Vmin threshold of the sequential logic during a test mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a logic to provide a data on a data node; a selector coupled to the data node and one of a supply node or a ground node, the selector having an output node; a flip-flop having a data input, an output, and a clock input, wherein the output node of the selector is coupled to the data input; and a comparator having a first input coupled to the data input, and a second input coupled to the output of the sequential logic. - View Dependent Claims (16, 17, 18)
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19. A system comprising:
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a memory, a processor coupled to the memory, the processor including a Vmin retention detector apparatus which comprises; a logic to provide a data on a data node; a selector coupled to the data node and one of a supply node or a ground node, the selector having an output node; a flip-flop having a data input, an output, and a clock input, wherein the output node of the selector is coupled to the data input; and a comparator having a first input coupled to the data input, and a second input coupled to the output of the sequential logic; and a wireless interface to allow the processor to communicate with another device. - View Dependent Claims (20)
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Specification