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Semiconductor device, battery monitoring system, and semiconductor device diagnosing method

  • US 10,451,680 B2
  • Filed: 12/21/2016
  • Issued: 10/22/2019
  • Est. Priority Date: 12/25/2015
  • Status: Active Grant
First Claim
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1. A battery monitoring integrated circuit (IC) comprising:

  • an input section to which a first voltage is input from a battery cell;

    a boosting section including one end to which the first voltage from the input section is input, and another end that, based on a control signal from a control section, outputs the first voltage or a second voltage boosted from the first voltage as a power supply voltage;

    a comparison section including an output section, a first input section connected to the input section and the one end of the boosting section, and a second input section connected to the another end of the boosting section, the comparison section configured to output a voltage from the output section that corresponds to a difference between voltages input to the first input section and the second input section;

    a first buffer section that is driven by the power supply voltage, that is connected to the another end of the boosting section, and that includes an input terminal to which the power supply voltage from the another end of the boosting section is input and an output terminal connected to the second input section of the comparison section;

    a first bypass section that includes a first switch connecting the input and output terminals of the first buffer section;

    a second buffer section that is driven by the power supply voltage, that is connected to the one end of the boosting section, and that includes an input terminal to which the power supply voltage from the one end of the boosting section is input and an output terminal connected to the first input section of the comparison section;

    a second bypass section that includes a second switch connecting the input and output terminals of the second buffer section;

    a first series element section, connected between the boosting section and the second buffer section, that includes a first resistance element and a third switch connected in series, the first series element section including one end connected directly to the input section and the one end of the boosting section, and including another end connected to the input terminal of the second buffer section; and

    a second series element section, connected between the boosting section and the first buffer section, that includes a second resistance element and a fourth switch connected in series, the second series element section including one end connected directly to the another end of the boosting section, and including another end connected to the input terminal of the first buffer section.

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