Source driver and operation method thereof

• US 10,452,088 B1
• Filed: 03/28/2019
• Issued: 10/22/2019
• Est. Priority Date: 03/28/2019
• Status: Active Grant

• Current Assignee: Himax Technologies Ltd. (Himax Technologies Incorporated)
• Original Assignee: Himax Technologies Ltd. (Himax Technologies Incorporated)
• Inventors: Chien, Chia-Chu
• Primary Examiner(s): Berhane, Adolf D
• Assistant Examiner(s): Demisse, Afework S
• Application Number:
  US16/367,241
• Time in Patent Office: 208 Days
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence

Abstract

A source driver and an operation method thereof are provided. The source driver includes an output buffer, a feedback switch, and a feedback voltage generating circuit. The output buffer receives the input voltage and produces an output voltage. The first terminal and the second terminal of the feedback switch are respectively coupled to the input terminal and the output terminal of the output buffer. During an overdrive period, the feedback switch is turned off, and the feedback voltage generating circuit outputs a feedback voltage to the output buffer. The feedback voltage is lower than the output voltage when the input voltage is in a rising mode. The feedback voltage is higher than the output voltage when the input voltage is in a falling mode. During a normal driving period, the feedback switch is turned on, and the feedback voltage generating circuit does not output the feedback voltage.

Claims

1. A source driver, comprising:

an output buffer, having a first input terminal to receive an input voltage, wherein an output terminal of the output buffer is configured to generate an output voltage to a data line of a display panel;

a feedback switch, having a first terminal and a second terminal respectively coupled to a second input terminal of the output buffer and the output terminal of the output buffer, wherein the feedback switch is turned off during an overdrive period, and the feedback switch is turned on during a normal driving period; and

a feedback voltage generating circuit, configured to generate and output a feedback voltage related to the output voltage to the second input terminal of the output buffer during the overdrive period, wherein the feedback voltage is not output to the second input terminal of the output buffer during the normal driving period, the feedback voltage is lower than the output voltage when the input voltage is in a rising mode, and the feedback voltage is higher than the output voltage when the input voltage is in a falling mode.

2. The source driver as claimed in claim 1, further comprising:

a digital to analog converter, coupled to the first input terminal of the output buffer, configured to convert a current pixel data to the input voltage, and output the input voltage to the first input terminal of the output buffer;

wherein “

the input voltage is in the rising mode”

is defined as “

the input voltage corresponding to the current pixel data is greater than the input voltage corresponding to a prior pixel data”

, and “

the input voltage is in the falling mode”

is defined as “

the input voltage corresponding to the current pixel data is smaller than the input voltage corresponding to the prior pixel data”

.

3. The source driver as claimed in claim 1, wherein the data line is coupled to a near pixel circuit and a far pixel circuit of the display panel, the distance from the near pixel circuit to the source driver is smaller than the distance from the far pixel circuit to the source driver, and the overdrive period related to the near pixel circuit is smaller than the overdrive period related to the far pixel circuit.

4. The source driver as claimed in claim 1, wherein the feedback voltage generating circuit comprises:

a first switch, having a first terminal coupled to the output terminal of the output buffer, wherein the first switch is turned on during the overdrive period and the first switch is turned off during the normal driving period;

a second switch, having a first terminal coupled to the second input terminal of the output buffer, wherein the second switch is turned on during the overdrive period, and the second switch is turned off during the normal driving period;

a first voltage-dividing resistor, having a first terminal coupled to a second terminal of the first switch, wherein a second terminal of the first voltage-dividing resistor is coupled to a second terminal of the second switch; and

a resistance circuit, coupled to the second terminal of the first voltage-dividing resistor.

5. The source driver as claimed in claim 4, wherein the resistance circuit comprises:

a second voltage-dividing resistor, having a first terminal coupled to the second terminal of the first voltage-dividing resistor;

a third switch, having a first terminal coupled to a second terminal of the second voltage-dividing resistor, wherein a second terminal of the third switch is coupled to a reference voltage, the reference voltage is lower than the output voltage, the third switch is turned on when the input voltage is in the rising mode, and the third switch is turned off when the input voltage is in the falling mode; and

a fourth switch, having a first terminal coupled to the second terminal of the second voltage-dividing resistor, wherein a second terminal of the fourth switch is coupled to a system voltage, the system voltage is higher than the output voltage, the fourth switch is turned off when the input voltage is in the rising mode, and the fourth switch is turned on when the input voltage is in the falling mode.

6. The source driver as claimed in claim 4, wherein the resistance circuit comprises:

a third switch, having a first terminal coupled to the second terminal of the first voltage-dividing resistor, wherein the third switch is turned on when the input voltage is in the rising mode, and the third switch is turned off when the input voltage is in the falling mode;

a second voltage-dividing resistor, having a first terminal coupled to a second terminal of the third switch, wherein a second terminal of the second voltage-dividing resistor is coupled to a reference voltage, and the reference voltage is lower than the output voltage;

a fourth switch, having a first terminal coupled to the second terminal of the first voltage-dividing resistor, wherein the fourth switch is turned off when the input voltage is in the rising mode, and the fourth switch is turned on when the input voltage is in the falling mode; and

a third voltage-dividing resistor, having a first terminal coupled to a second terminal of the fourth switch, wherein a second terminal of the third voltage-dividing resistor is coupled to a system voltage, and the system voltage is higher than the output voltage.

7. The source driver as claimed in claim 4, wherein the resistance circuit comprises:

a second voltage-dividing resistor, having a first terminal coupled to the second terminal of the first voltage-dividing resistor; and

a digital to analog circuit, having an output terminal coupled to a second terminal of the second voltage-dividing resistor, configured to convert a prior pixel data to a prior voltage, and output the prior voltage to the second terminal of the second voltage-dividing resistor.

8. The source driver as claimed in claim 7, wherein the digital to analog circuit comprises:

a digital to analog converter, having an input terminal configured to receive the prior pixel data; and

a unity-gain buffer, having an input terminal coupled to an output terminal of the digital to analog converter, wherein an output terminal of the unity-gain buffer is coupled to the second terminal of the second voltage-dividing resistor to supply the prior voltage.

9. The source driver as claimed in claim 4, wherein the resistance circuit comprises:

a third switch, having a first terminal coupled to the second terminal of the first voltage-dividing resistor, wherein the third switch is turned on when the input voltage is in the rising mode, and the third switch is turned off when the input voltage is in the falling mode;

a second voltage-dividing resistor, having a first terminal coupled to a second terminal of the third switch;

a fourth switch, having a first terminal coupled to the second terminal of the first voltage-dividing resistor, wherein the fourth switch is turned off when the input voltage is in the rising mode, and the fourth switch is turned on when the input voltage is in the falling mode;

a third voltage-dividing resistor, having a first terminal coupled to a second terminal of the fourth switch; and

a digital to analog circuit, having an output terminal coupled to a second terminal of the second voltage-dividing resistor and a second terminal of the third voltage-dividing resistor, configured to convert a prior pixel data to a prior voltage, and output the prior voltage to the second terminal of the second voltage-dividing resistor and the second terminal of the third voltage-dividing resistor.

10. The source driver as claimed in claim 1, wherein the output buffer comprises an operational amplifier.

11. An operation method of a source driver, comprising:

receiving an input voltage by a first input terminal of an output buffer, and generating an output voltage to a data line of a display panel from an output terminal of the output buffer;

turning off a feedback switch during an overdrive period, wherein a first terminal and a second terminal of the feedback switch are respectively coupled to a second input terminal of the output buffer and the output terminal of the output buffer;

generating and outputting a feedback voltage related to the output voltage from a feedback voltage generating circuit to the second input terminal of the output buffer during the overdrive period, wherein the feedback voltage is lower than the output voltage when the input voltage is in a rising mode, and the feedback voltage is higher than the output voltage when the input voltage is in a falling mode;

turning on the feedback switch during a normal driving period; and

not outputting the feedback voltage to the second input terminal of the output buffer from the feedback voltage generating circuit during the normal driving period.

12. The operation method as claimed in claim 11, further comprising:

converting a current pixel data to the input voltage by a digital to analog converter; and

outputting the input voltage to the first input terminal of the output buffer by the digital to analog converter;

wherein “

the input voltage is in the rising mode”

is defined as “

the input voltage corresponding to the current pixel data is greater than the input voltage corresponding to a prior pixel data”

, and “

the input voltage is in the falling mode”

is defined as “

the input voltage corresponding to the current pixel data is smaller than the input voltage corresponding to the prior pixel data”

.

13. The operation method as claimed in claim 11, wherein the data line is coupled to a near pixel circuit and a far pixel circuit of the display panel, the distance from the near pixel circuit to the source driver is smaller than the distance from the far pixel circuit to the source driver, and the overdrive period related to the near pixel circuit is smaller than the overdrive period related to the far pixel circuit.

14. The operation method as claimed in claim 11, further comprising:

turning on a first switch during the overdrive period, wherein a first terminal of the first switch is coupled to the output terminal of the output buffer, and a second terminal of the first switch is coupled to a first terminal of a first voltage-dividing resistor;

turning on a second switch during the overdrive period, wherein a first terminal of the second switch is coupled to the second input terminal of the output buffer, and a second terminal of the second switch is coupled to a second terminal of a first voltage-dividing resistor and a resistance circuit;

turning off the first switch during the normal driving period; and

turning off the second switch during the normal driving period.

15. The operation method as claimed in claim 14, further comprising:

turning on a third switch when the input voltage is in the rising mode, wherein a first terminal of a second voltage-dividing resistor is coupled to the second terminal of the first voltage-dividing resistor, a first terminal of the third switch is coupled to a second terminal of the second voltage-dividing resistor, a second terminal of the third switch is coupled to a reference voltage, and the reference voltage is lower than the output voltage;

turning off a fourth switch when the input voltage is in the rising mode, wherein a first terminal of the fourth switch is coupled to the second terminal of the second voltage-dividing resistor, a second terminal of the fourth switch is coupled to a system voltage, and the system voltage is higher than the output voltage;

turning off the third switch when the input voltage is in the falling mode; and

turning on the fourth switch when the input voltage is in the falling mode.

16. The operation method as claimed in claim 14, further comprising:

turning on a third switch when the input voltage is in the rising mode, wherein a first terminal of the third switch is coupled to the second terminal of the first voltage-dividing resistor, a second terminal of the third switch is coupled to a first terminal of a second voltage-dividing resistor, a second terminal of the second voltage-dividing resistor is coupled to a reference voltage, and the reference voltage is lower than the output voltage;

turning off a fourth switch when the input voltage is in the rising mode, wherein a first terminal of the fourth switch is coupled to the second terminal of the first voltage-dividing resistor, a second terminal of the fourth switch is coupled to a first terminal of a third voltage-dividing resistor, a second terminal of the third voltage-dividing resistor is coupled to a system voltage, and the system voltage is higher than the output voltage;

turning off the third switch when the input voltage is in the falling mode; and

turning on the fourth switch when the input voltage is in the falling mode.

17. The operation method as claimed in claim 14, further comprising:

converting a prior pixel data to a prior voltage by a digital to analog circuit; and

outputting the prior voltage to a second terminal of a second voltage-dividing resistor by the digital to analog circuit, wherein a first terminal of the second voltage-dividing resistor is coupled to the second terminal of the first voltage-dividing resistor.

18. The operation method as claimed in claim 17, further comprising:

receiving the prior pixel data by an output terminal of a digital to analog converter, wherein an output terminal of a unity-gain buffer is coupled to an output terminal of the digital to analog converter; and

supplying the prior voltage to the second terminal of the second voltage-dividing resistor by an output terminal of the unity-gain buffer.

19. The operation method as claimed in claim 14, further comprising:

turning on a third switch when the input voltage is in the rising mode, wherein a first terminal of the third switch is coupled to the second terminal of the first voltage-dividing resistor, and a second terminal of the third switch is coupled to a first terminal of a second voltage-dividing resistor;

turning off a fourth switch when the input voltage is in the rising mode, wherein a first terminal of the fourth switch is coupled to the second terminal of the first voltage-dividing resistor, and a second terminal of the fourth switch is coupled to a first terminal of a third voltage-dividing resistor;

turning off the third switch when the input voltage is in the falling mode;

turning on the fourth switch when the input voltage is in the falling mode;

converting a prior pixel data to a prior voltage by a digital to analog circuit; and

outputting the prior voltage to a second terminal of the second voltage-dividing resistor and a second terminal of the third voltage-dividing resistor by the digital to analog circuit.