Display device and electronic device

• US 10,452,218 B2
• Filed: 01/12/2018
• Issued: 10/22/2019
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamamoto, Roh, Uochi, Hideki
• Primary Examiner(s): Sasinowski, Andrew
• Application Number:
  US15/870,141
• Publication Number:
  US 20180224961A1
• Time in Patent Office: 648 Days
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0613 The adjustment depending on the type of the information to be displayed
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display device with less power consumption. The display device operates in a still image display period and a moving image display period, and includes a receiving circuit having a function of receiving an image signal, a driver circuit having a function of driving a display portion, and the display portion having a function of displaying an image. The display portion displays an image at a frame frequency of less than or equal to 1 Hz in the still image display period. The receiving circuit stops receiving an image signal in the still image display period. Switching from the still image display period to the moving image display period is accurately performed by an external signal.

Claims

1. A display device comprising:

a display panel comprising a display portion comprising a pixel; and

a receiving circuit configured to receive a serial digital image signal for the display panel,

wherein the pixel comprises a transistor,

wherein the transistor comprises a semiconductor layer comprising an oxide semiconductor,

wherein the receiving circuit comprises a low-voltage differential signaling receiver,

wherein the low-voltage differential signaling receiver comprises an operational amplifier,

wherein the display panel further comprises a driver circuit,

wherein the driver circuit is electrically connected to the display portion, and

wherein the receiving circuit is configured to stop supply of a bias current to the operational amplifier while an operation of the driver circuit is stopped.

2. The display device according to claim 1,

wherein the receiving circuit is configured to stop supply of the bias current to the operational amplifier while the display portion displays an image at a frame frequency of less than or equal to 1 Hz.

3. The display device according to claim 1,

wherein the driver circuit is configured such that the operation of the driver circuit is stopped during a still image display period.

4. The display device according to claim 1,

wherein the oxide semiconductor comprises indium, gallium, zinc and oxygen.

5. A display device comprising:

a display panel comprising a display portion comprising a pixel; and

a receiving circuit configured to receive a serial digital image signal for the display panel,

wherein the pixel comprises a transistor and a liquid crystal element,

wherein one of a source and a drain of the transistor is electrically connected to the liquid crystal element,

wherein the other of the source and the drain of the transistor is electrically connected to a signal line,

wherein the transistor comprises a semiconductor layer comprising an oxide semiconductor,

wherein the receiving circuit comprises a low-voltage differential signaling receiver,

wherein the low-voltage differential signaling receiver comprises an operational amplifier,

wherein the display panel further comprises a driver circuit,

wherein the driver circuit is electrically connected to the display portion, and

wherein the receiving circuit is configured to stop supply of a bias current to the operational amplifier while an operation of the driver circuit is stopped.

6. The display device according to claim 5,

wherein the receiving circuit is configured to stop supply of the bias current to the operational amplifier while the display portion displays an image at a frame frequency of less than or equal to 1 Hz.

7. The display device according to claim 5,

wherein the driver circuit is configured such that the operation of the driver circuit is stopped during a still image display period.

8. The display device according to claim 5,

wherein the oxide semiconductor comprises indium, gallium, zinc and oxygen.

9. A display device comprising:

a display panel comprising a display portion comprising a pixel;

a receiving circuit configured to receive a serial digital image signal for the display panel; and

an image processing circuit comprising a memory circuit, a comparison circuit and a control circuit,

wherein the pixel comprises a transistor and a liquid crystal element,

wherein the receiving circuit comprises a low-voltage differential signaling receiver,

wherein the low-voltage differential signaling receiver comprise an operational amplifier comprising a non-inverted signal input terminal and an inverted signal input terminal,

wherein the operational amplifier is configured such that the serial digital image signal and an inverted signal of the serial digital image signal are input to the non-inverted signal input terminal and the inverted signal input terminal, respectively,

wherein the operational amplifier is configured such that supply of a bias current to the operational amplifier is stopped in accordance with a signal output from the control circuit,

wherein the memory circuit is configured to store a first image signal for a first frame period and a second image signal for a second frame period, and

wherein the comparison circuit is configured to compare the first image signal and the second image signal and detect whether the first image signal is different from the second image signal.

10. The display device according to claim 9,

wherein the receiving circuit is configured to stop the supply of the bias current to the operational amplifier while the display portion displays an image at a frame frequency of less than or equal to 1 Hz.

11. The display device according to claim 9,

wherein the display panel further comprises a driver circuit,

wherein the driver circuit is electrically connected to the display portion, and

wherein the receiving circuit is configured to stop the supply of the bias current to the operational amplifier while an operation of the driver circuit is stopped.

12. The display device according to claim 11,

wherein the driver circuit is configured such that the operation of the driver circuit is stopped during a still image display period.

13. The display device according to claim 9,

wherein the transistor comprises a semiconductor layer comprising indium, gallium, zinc and oxygen.