System to reduce directory information storage

• US 10,452,272 B2
• Filed: 12/27/2016
• Issued: 10/22/2019
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Arteris Incorporated
• Original Assignee: Arteris Incorporated
• Inventors: Gaikwad, Parimal
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Li, Hewy H
• Application Number:
  US15/390,752
• Publication Number:
  US 20170192689A1
• Time in Patent Office: 1,029 Days
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting address bits thereby allowing subsystems to avoid transmitting, storing, and operating upon excessive address information.

Claims

1. A system-on-chip (SoC) comprising:

a transport network;

a plurality of masters communicating using the transport network;

a directory communicating using the transport network, the directory having a default encoding stored in a directory table;

memory, which includes coherent memory regions, the memory being accessed via and communicating through the transport network;

a first logic unit, communicating through the transport network, for tracking information committed to the directory and updating one counter selected from a plurality of counters for one pattern that is selected from a plurality of patterns, the one pattern being associated with the information committed to the directory; and

a second logic unit, communicating through the transport network, for updating the directory with an updated encoding

wherein the first logic unit uses a control bit of the directory to determine which of an old encoding table and a new encoding table will be used by the second logic unit to update the directory.

2. The SoC of claim 1, wherein the first logic unit includes:

the old encoding table; and

the new encoding table,

the new encoding table and the old encoding table are for a group of patterns selected from the plurality of patterns, wherein the group of patterns are a limited set of patterns that are tracked within and can be updated with a new group of patterns.

3. The SoC of claim 2, wherein the directory further includes a control bit entry for tracking status information for each encoding pattern stored in the directory.

4. The SoC of claim 1, wherein the second logic unit includes:

a digital control unit for generating a signal for updating the directory based on information collected at the first logic unit; and

a defragment control logic unit for updating the directory with the updated encoding.

5. The SoC of claim 1 further comprising a third logic unit in communication with the second logic unit, the third logic unit receives a signal from the second logic unit and updates the directory with the update encoding and defragments the directory.

6. A system-on-chip (SoC) comprising:

a transport network;

a plurality of masters communicating using the transport network;

a directory communicating using the transport network, the directory having a default encoding stored in a directory table, wherein the directory further includes a control bit for tracking status information for each encoding pattern stored in the directory;

memory, which includes coherent memory regions, the memory being accessed via and communicating through the transport network;

a first logic unit, communicating through the transport network, for tracking information committed to the directory and updating one counter selected from a plurality of counters for one pattern that is selected from a plurality of patterns, the one pattern being associated with the information committed to the directory wherein the first logic unit includes;

an old encoding table; and

a new encoding table,

the new encoding table and the old encoding table are for a group of patterns selected from the plurality of patterns, wherein the group of patterns are a limited set of patterns that are tracked within and can be updated with a new group of patterns; and

a second logic unit, communicating through the transport network, for updating the directory with an updated encoding,

wherein the first logic unit includes two tables that correlate to the control bit of the directory to allow the control bit to determine which of the old encoding table and the new encoding table will be used by the second logic unit to update the directory.