Memory management

• US 10,452,282 B2
• Filed: 04/07/2017
• Issued: 10/22/2019
• Est. Priority Date: 04/07/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Muchherla, Kishore K., Ratnam, Sampath K., Feeley, Peter, Miller, Michael G., Thomson, Preston A., Padilla, Renato C., Malshe, Ashutosh
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Dare, Ryan
• Application Number:
  US15/482,337
• Publication Number:
  US 20180293003A1
• Time in Patent Office: 928 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Claims

1. An apparatus, comprising:

an array of memory cells comprising a plurality of mixed mode blocks; and

a controller configured to;

monitor respective erase counts corresponding to the plurality of mixed mode blocks;

responsive to erasing a particular mixed mode block of the plurality of mixed mode blocks, incrementing an erase count corresponding to the particular block by different amounts based on whether the particular mixed mode block was erased in a single level cell (SLC) mode or an extra level cell (XLC) mode; and

as part of a garbage collection process;

allocate a first mixed mode block among the plurality of mixed mode blocks to a first pool of mixed mode blocks based on the respective erase count for the first mixed mode block;

allocate a second mixed mode block among the plurality of mixed mode blocks to a second pool of mixed mode blocks based on the respective erase count for the second mixed mode block;

allocate a third mixed mode block among the plurality of mixed mode blocks to a third pool of mixed mode blocks based on the respective erase count for the third mixed mode block; and

determine whether to move the third mixed mode block from the third pool of mixed mode blocks to one of the first pool of mixed mode blocks and the second pool of mixed mode blocks by comparing the respective erase count for the third mixed mode block with respective erase counts for a number of other mixed mode blocks within the third pool of mixed mode blocks.

2. The apparatus of claim 1, wherein the first mixed mode block has a lower respective erase count than the respective erase count of the second mixed mode block and the respective erase count of the third mixed mode block.

3. The apparatus of claim 1, wherein the controller is configured to:

erase blocks in the first pool of mixed mode blocks in the (SLC) mode;

erase blocks in the second pool of mixed mode blocks in the (XLC) mode; and

store mixed mode blocks that are ready to be erased in the third pool of mixed mode blocks.

4. The apparatus of claim 3, wherein the controller is further configured to prioritize writing data to blocks that have been erased in the XLC mode.

5. The apparatus of claim 1, wherein a number of blocks in the third pool of mixed mode blocks is less than a number of blocks in the second pool of mixed mode blocks.