Increasing granularity of dirty bit information in hardware assisted memory management systems

• US 10,452,559 B2
• Filed: 09/18/2017
• Issued: 10/22/2019
• Est. Priority Date: 07/18/2011
• Status: Active Grant

• Current Assignee: Vmware LLC (Broadcom, Inc.)
• Original Assignee: VMware, Inc. (Broadcom, Inc.)
• Inventors: Serebrin, Benjamin C., Mehta, Bhavesh
• Primary Examiner(s): Sain, Gautam
• Application Number:
  US15/708,063
• Publication Number:
  US 20180004679A1
• Time in Patent Office: 764 Days
• Field of Search: 711 6, 711200
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2^M)-th of a memory page.

Claims

1. A memory management unit (MMU) of a computer system having virtual machines instantiated therein, wherein the MMU comprises:

a guest page walker that accesses a set of first mapping tables that are hierarchically arranged and define mappings between guest virtual addresses and guest physical addresses and a set of second mapping tables that are hierarchically arranged and define mappings between guest physical addresses and machine memory addresses, the set of second mapping tables including a root table and a plurality of bottom-level tables, and that uses a pointer to each table and the guest virtual addresses to form a guest physical address for translation to a machine memory address; and

a nested page walker that translates the guest physical address for translation into a machine memory address,

wherein each of a plurality of entries of the bottom-level tables references a machine memory page in common with at least one other entry of the bottom-level tables, and each of the plurality of entries of the bottom-level tables includes a status bit value that indicates whether or not data stored in the machine memory page referenced by said entry is dirty or not, and said status bit values of at least two entries of the bottom-level tables that reference the same machine memory page are different.

2. The MMU of claim 1, wherein said at least two entries of the bottom-level tables that reference the same machine memory page are associated with at least two different guest physical addresses.

3. The MMU of claim 2, wherein the two different guest physical addresses that reference the same memory page include

a first guest physical address that references one of the first mapping tables and

a second guest physical address that differs from the first guest physical address by at least one bit value.

4. The MMU of claim 3, wherein the first guest physical address references a root table of the first mapping tables.

5. The MMU of claim 3, wherein the first guest physical address references an intermediate-level table of the first mapping tables.

6. The MMU of claim 3, wherein the first guest physical address references a bottom-level table of the first mapping tables.

7. The MMU of claim 2, wherein the two different guest physical addresses that reference the same memory page include a first guest physical address that references a page of data and a second guest physical address that differs from the first guest physical address by at least one bit value.

8. A method of mapping guest virtual addresses to machine memory addresses in a computer system having virtual machines instantiated therein, comprising:

receiving a guest virtual address to be mapped;

traversing guest page tables using portions of the guest virtual address to obtain a guest physical address corresponding to the guest virtual address;

modifying a binary representation of the guest physical address corresponding to the guest virtual address by copying the value of a first bit of the binary representation to a second bit of the binary representation, wherein the second bit is more significant than the first bit; and

translating the guest physical address corresponding to the guest virtual address to a machine memory address using the modified binary representation.

9. The method of claim 8, wherein the guest physical address is translated to the machine memory address using nested page tables.

10. The method of claim 8, wherein said traversing includes:

generating a guest physical address corresponding to one of the guest page tables;

modifying a binary representation of the guest physical address corresponding to one of the guest page tables by copying the value of a first bit of the binary representation to a second bit of the binary representation, wherein the second bit is more significant than the first bit; and

traversing the nested page tables to translate the guest physical address corresponding to one of the guest page tables to a machine memory address.

11. The method of claim 10, wherein bit positions of the first and second bits in the modified binary representation of the guest physical address corresponding to the guest virtual address are the same as bit positions of the first and second bits in the modified binary representation of the guest physical address corresponding to one of the guest page tables.

12. The method of claim 8, wherein the binary representation of the guest physical address corresponding to the guest virtual address is further modified by copying the value of one or more additional bits of the binary representation to one or more additional bits of the binary representation that are more significant.

13. The method of claim 8, further comprising:

prior to said modifying, verifying that the second bit has a value of zero.

14. The method of claim 8, further comprising:

adding a mapping of the guest virtual address to the machine memory address as an entry to a translation lookaside buffer.