Storing secure state information in translation lookaside buffer cache lines
First Claim
1. A system configured to manage access requests to protected regions of memory, the system comprising:
- a system-on-chip that includes a plurality of processing units and a first memory, wherein;
the first memory includes a page table having a plurality of page table entries; and
a first parallel processing unit is included in the plurality of the processing units, wherein the first parallel processing unit includes an internal memory and a memory management unit, and wherein the memory management unit is coupled to the first memory and configured to;
receive a first request to translate a first virtual memory address to a first physical memory address;
select a first page table entry included in the plurality of page table entries based on the first virtual memory address;
translate the first virtual memory address to the first physical memory address based on the first page table entry;
determine first secure state information based on the first physical memory address;
store the first page table entry and the first secure state information in a first data cache line included in a first translation lookaside buffer associated with a first client, wherein the first secure state information originates from the internal memory and specifies at least one client authorized to access the first physical memory address; and
generate a first memory access response based on the first page table entry and the first secure state information.
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Accused Products
Abstract
One embodiment of the present invention includes a memory management unit (MMU) that is configured to efficiently process requests to access memory that includes protected regions. Upon receiving an initial request via a virtual address (VA), the MMU translates the VA to a physical address (PA) based on page table entries (PTEs) and gates the response based on page-specific secure state information. To thwart software-based attempts to illicitly access the protected regions, the secure state information is not stored in page tables. However, to expedite subsequent requests, after the MMU identifies the PTE and the corresponding secure state information, the MMU stores both the PTE and the secure state information as a cache line in a translation lookaside buffer. Advantageously, the disclosed embodiments protect data in the protected regions from security risks associated with software-based protection schemes without incurring the performance degradation associated with hardware-based “carve-out” memory protection schemes.
5 Citations
24 Claims
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1. A system configured to manage access requests to protected regions of memory, the system comprising:
a system-on-chip that includes a plurality of processing units and a first memory, wherein; the first memory includes a page table having a plurality of page table entries; and a first parallel processing unit is included in the plurality of the processing units, wherein the first parallel processing unit includes an internal memory and a memory management unit, and wherein the memory management unit is coupled to the first memory and configured to; receive a first request to translate a first virtual memory address to a first physical memory address; select a first page table entry included in the plurality of page table entries based on the first virtual memory address; translate the first virtual memory address to the first physical memory address based on the first page table entry; determine first secure state information based on the first physical memory address; store the first page table entry and the first secure state information in a first data cache line included in a first translation lookaside buffer associated with a first client, wherein the first secure state information originates from the internal memory and specifies at least one client authorized to access the first physical memory address; and generate a first memory access response based on the first page table entry and the first secure state information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 19, 20, 21, 22, 23, 24)
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11. A method for managing access requests to protected regions of memory, the method comprising:
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receiving a first request to translate a first virtual memory address to a first physical memory address; selecting a first page table entry included in a page table having a plurality of page table entries based on the first virtual memory address, the page table being stored to a first memory coupled to a memory management unit of a first parallel processing unit; translating the first virtual memory address to the first physical memory address based on the first page table entry; determining first secure state information based on the first physical memory address; storing the first page table entry and the first secure state information in a first data cache line included in a first translation lookaside buffer associated with a first client, wherein a system-on-chip includes a plurality of processing units and the first memory and the first parallel processing unit is included in the plurality of the processing units, wherein the first parallel processing unit further comprises an internal memory, wherein the first secure state information originates from the internal memory of the first parallel processing unit and specifies at least one client authorized to access the first physical memory address, and generating a first memory access response based on the first page table entry and the first secure state information. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification