Apparatus and methods for in data path compute operations
First Claim
1. An apparatus, comprising:
- a plurality of shared input/output (I/O) lines configured to selectably couple via sensing circuitry;
a first subrow of a row of an array of memory cells to a first compute component in a data path to move a first data value from the first subrow to the first compute component; and
a second subrow of the respective row to a second compute component in the data path to move a second data value from the second subrow to the second compute component; and
a controller configured to direct the first compute component to perform a compute operation on the first data value moved from the first subrow substantially simultaneously with movement of the second data value from the second subrow to the second compute component.
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Abstract
The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.
313 Citations
20 Claims
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1. An apparatus, comprising:
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a plurality of shared input/output (I/O) lines configured to selectably couple via sensing circuitry; a first subrow of a row of an array of memory cells to a first compute component in a data path to move a first data value from the first subrow to the first compute component; and a second subrow of the respective row to a second compute component in the data path to move a second data value from the second subrow to the second compute component; and a controller configured to direct the first compute component to perform a compute operation on the first data value moved from the first subrow substantially simultaneously with movement of the second data value from the second subrow to the second compute component. - View Dependent Claims (2, 3, 4, 5)
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6. A system, comprising:
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a host configured to generate instructions; a memory device coupled to the host and comprising; an array of memory cells configured to store operands; and a plurality of logic stripes in a data path for in data path compute operations, including a first logic stripe including a number of a plurality of first compute components that corresponds to a number of a plurality of memory cells of a first subrow of a row of the array; control circuitry configured to execute instructions from the host to direct; movement of a first data value from a first subrow of a first row of the array, via an input/output (I/O) line shared as a data path, to a first compute component of a first logic stripe in the data path; performance of a first operation on the first data value from the first subrow using the first compute component; and movement of a second data value, resulting from performance of the first operation, from the first logic stripe via connection circuitry to a second compute component of a second logic stripe in the data path. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for operating a memory device, comprising:
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performing a first operation on a data value moved from a memory cell in a first subrow in a first row of an array of memory cells to a first logic stripe for in data path compute operations; and moving the data value, to enable performance of a second operation thereon, to a selected second logic stripe via connection circuitry selectably coupling the first logic stripe and the second logic stripe. - View Dependent Claims (18, 19, 20)
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Specification