Semiconductor device

• US 10,452,588 B2
• Filed: 07/25/2017
• Issued: 10/22/2019
• Est. Priority Date: 08/23/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Ito, Mikihiko, Koyanagi, Masaru
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US15/658,901
• Publication Number:
  US 20180060265A1
• Time in Patent Office: 819 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor device includes first input/output circuits for a first channel, first input/output pads corresponding to the first input/output circuits, respectively, wherein the first input/output pads are aligned along and extends in a first direction, second input/output circuits for the first channel, second input/output pads corresponding to the second input/output circuits, respectively, wherein the second input/output pads are aligned along and extends in a second direction, and an input circuit between the first input/output pads and the second input/output pads, and connected to a memory to which the input circuit inputs data from the first input/output circuits and the second input/output circuits. The input circuit is positioned such that a first line extending perpendicular to the first direction from one of the first input/output pads and a second line extending perpendicular to the second direction from one of the second input/output pads intersect a portion of the input circuit.

Claims

1. A semiconductor device comprising:

a plurality of first input/output circuits for a first channel;

a plurality of first input/output pads respectively corresponding to the plurality of first input/output circuits and aligned with each other along a first direction;

a plurality of second input/output circuits for the first channel;

a plurality of second input/output pads respectively corresponding to the plurality of second input/output circuits and aligned with each other along a second direction;

a data input latch circuit positioned between the plurality of first input/output pads and the plurality of second input/output pads, wherein a straight line extending from one of the first input/output pads to one of the second input/output pads intersects each of the first and second directions and crosses the position of the data input latch circuit;

a first non-input/output circuit and a pad corresponding thereto that is aligned with the first input/output pads in the first direction; and

a second non-input/output circuit and a pad corresponding thereto that is aligned with the second input/output pads in the second direction, wherein

the first direction and the second direction are parallel,

the pad corresponding to the first non-input/output circuit is between at least two of the first input/output pads, and

the pad corresponding to the second non-input/output circuit is between at least two of the second input/output pads.

2. The semiconductor device according to claim 1, wherein the second non-input/output circuit is a read enable circuit.

3. A semiconductor device for transmitting and receiving a signal to and from a memory device, the semiconductor device comprising:

a plurality of first input/output circuits, each respectively having a first input/output pad for a first channel of the memory device arranged in a first row;

a plurality of second input/output circuits, each respectively having a second input/output pad for the first channel of the memory device arranged in a second row spaced from the first row in a first direction;

an input circuit positioned between the first and second rows in the first direction, the input circuit connected to the memory device and configured to input data received through the first and second input/output pads to the memory device, wherein at least two of the first input/output pads are at a first distance from the input circuit along the first direction and at least two of the second input/output pads are at the first distance from the input circuit along the first direction;

a first non-input/output circuit and a pad corresponding thereto that is aligned with the first input/output pads in the first row; and

a second non-input/output circuit and a pad corresponding thereto that is aligned with the second input/output pads in the second row, wherein

the first row and the second row extend in parallel,

the pad corresponding to the first non-input/output circuit is between at least two of the first input/output pads, and

the pad corresponding to the second non-input/output circuit is between at least two of the second input/output pads.

4. The semiconductor device according to claim 3, wherein the second non-input/output circuit is a read enable circuit.

5. A semiconductor device comprising:

a plurality of memory chips, each including a substrate and electrodes penetrating the substrate and formed with memory devices connected to the electrodes; and

an interface chip configured to transmit and receive data to and from the plurality of memory devices via the electrodes of the memory chips, wherein the plurality of memory chips includes a first memory chip stacked on the interface chip and a second memory chip stacked on the first memory chip, and

the interface chip includes;

a plurality of first input/output pads that are associated with a first channel provided between the first input/output pads and the memory chips and arranged in a first row;

a plurality of second input/output pads that are associated with the first channel and arranged in a second row; and

an input circuit between the first and second rows and connected to the memory chips to which the input circuit performs input of data received through the first and second input/output pads, wherein at least two of the first input/output pads are spaced from the input circuit by substantially the same distance and at least two of the second input/output pads are spaced from the input circuit by substantially the same distance.

6. The semiconductor device according to claim 5, wherein the first row and the second row extend in parallel.

7. The semiconductor device according to claim 6, further comprising:

a first non-input/output circuit and a pad corresponding thereto that is aligned with the first input/output pads in the first row; and

a second non-input/output circuit and a pad corresponding thereto that is aligned with the second input/output pads in the second row,

wherein the pad corresponding to the first non-input/output circuit is between at least two of the first input/output pads, and the pad corresponding to the second non-input/output circuit is between at least two of the second input/output pads.

8. The semiconductor device according to claim 6, further comprising:

a first non-input/output circuit and a pad corresponding thereto that is aligned with the first input/output pads in the first row, wherein the pad corresponding to the first non-input/output circuit is between at least two of the first input/output pads; and

a second non-input/output circuit and a pad corresponding thereto that is between the first input/output pads and the second input/output pads.

9. The semiconductor device according to claim 5, wherein the first row extends in a first direction and the second row extends in a second direction that crosses the first direction.

10. The semiconductor device according to claim 9, further comprising:

a first non-input/output circuit and a pad corresponding thereto that is aligned with the first input/output pads in the first row; and

a second non-input/output circuit and a pad corresponding thereto that is aligned with the second input/output pads in the second row,

wherein the pad corresponding to the first non-input/output circuit is between at least two of the first input/output pads, and the pad corresponding to the second non-input/output circuit is between at least two of the second input/output pads.