System and method for memory synchronization of a multi-core system

• US 10,452,686 B2
• Filed: 08/04/2017
• Issued: 10/22/2019
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Iliopoulos, Antonios, Goikhman, Shay, Levy, Eliezer
• Primary Examiner(s): Dudek, Jr., Edward J
• Assistant Examiner(s): Li, Sidney
• Application Number:
  US15/669,547
• Publication Number:
  US 20170337256A1
• Time in Patent Office: 809 Days
• Field of Search: 711133
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 16/2315 Optimistic concurrency control
• CPC Class Codes: G06F 16/27 Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
• CPC Class Codes: G06F 16/283 Multi-dimensional databases or data warehouses, e.g. MOLAP or ROLAP
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

A system for memory synchronization of a multi-core system is provided, the system comprising: an assigning module which is configured to assign at least one memory partition to at least one core of the multi-core system; a mapping module which is configured to provide information for translation lookaside buffer shootdown for the multi-core system leveraged by sending an interrupt to the at least one core of the multi-core system, if a page table entry associated with the memory partition assigned to the at least one core is modified; and an interface module which is configured to provide an interface to the assigning module from user-space.

Claims

1. A system for memory synchronization for a multi-core system comprising multiple cores, the system comprising:

a memory, and a processor configured to execute instructions stored in the memory to;

bind, via an interface, at least one memory partition to a particular core of the multiple cores;

control the binding of the at least one memory partition to the particular core using a set of system calls; and

send a translation lookaside buffer (TLB) shootdown request via an inter-processor interrupt (IPI) only to the particular core bound to the at least one memory partition when a page table entry associated with the at least one memory partition is modified.

2. The system according to claim 1, wherein the TLB shootdown request is sent during a copy-on-write page sharing of the at least one memory partition.

3. The system according to claim 1, wherein the processor uses the set of system calls to receive the TLB shootdown information.

4. A database, comprising

a multi-core system with multiple cores;

a memory system with multiple memory partitions; and

a system for memory synchronization of the multi-core system, the system comprising a processor configured to execute instructions stored in a memory to;

operate as an assigning module configured to bind, via an interface, at least one memory partition to a particular core of the multiple cores;

operate as a mapping module configured to send a TLB shootdown request via an inter-processor interrupt (IPI) only to the particular core bound to the at least one memory partition when a page table entry associated with the at least one memory partition is modified; and

operate as an interface module which is configured to control the binding of the at least one memory partition to the particular core using a set of system calls.

5. The database according to claim 4, wherein the database is a hybrid online transactional processing and online analytical processing database.

6. The database according to claim 5, wherein the database is configured to perform online transaction processing by ensuring that at least one online transactional processing thread operates on one or more of the at least one memory partition.

7. The database according to one of claim 4, wherein the database is enabled to provide a controlled dispatching of the TLB shootdown by using a data structure indicating which of the multiple cores is bound to which of the at least one memory partition.

8. The database according to claim 4, wherein the interface module is configured to adapt the TLB shootdown by information as received by using the set of system calls.

9. A method for memory synchronization for a multi-core system comprising multiple cores, the method comprising:

binding, via an interface, at least one memory partition to a particular core of the multiple cores;

sending a translation lookaside buffer (TLB) shootdown request via an inter-processor interrupt (IPI) only to the particular core bound to the at least one memory partition when a page table entry associated with the at least one memory partition is modified; and

controlling the binding of the at least one memory partition to the particular core using a set of system calls.

10. The method according to claim 9, wherein the step of sending the TLB shootdown request is performed during a copy-on-write page sharing of the at least one memory partition.

11. The method according to claim 9, wherein the TLB shootdown information is received by using the set of system calls.

12. The method of claim 10 wherein program instructions that define the operations to be performed by a processor are stored in a non-transitory computer readable media.