Routing of nets of an integrated circuit

• US 10,452,801 B2
• Filed: 11/14/2015
• Issued: 10/22/2019
• Est. Priority Date: 06/17/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Beck, Manuel, Peyer, Sven, Schulte, Christian, Ziegler, Wolfram
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Lin, Aric
• Application Number:
  US14/941,579
• Publication Number:
  US 20160371418A1
• Time in Patent Office: 1,438 Days
• Field of Search: None
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

Claims

1. A computer-implemented method of generating layouts of nets connecting source cells and sink cells for use in fabrication of an integrated circuit, the computer-implemented method comprising:

receiving a routing specification for the nets of the integrated circuit and a target performance parameter for each of the nets, the target performance parameters for each of the nets specifying a propagation property of electrical signals in the nets, comprising a time of error free propagation of the electrical signals in the nets, and a slew rate;

generating layouts of the nets according to the routing specification;

generating an actual performance parameter for each of the nets in the layouts, the actual performance parameters specifying a calculated actual propagation property of electrical signals in the nets and a calculated actual slew rate;

generating deviation parameters, each of the deviation parameters being indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter; and

repetitively executing the following;

generating new layouts of the nets according to the routing specification, the new layouts being generated based on a topological constraint in combination with a ranking of an order of the generation of the layouts, the order of the generation being determined by the ranking of each net, and determining the topological constraint for the new layouts by generating a monotonically increasing function of a respective deviation parameter, the ranking being performed according to the respective deviation parameter of each net, wherein the ranking is described by a monotonically decreasing function of the respective deviation parameter, wherein the monotonically decreasing function is a step function, and wherein a slack value and the slew rate are arguments of the monotonically decreasing function, the generation of the new layouts of the nets according to the routing specification being performed first for the nets having a highest ranking, the nets with the highest ranking having highest deviation parameters of the deviation parameters, and determining the topological constraint for the new layout comprises generating a monotonically increasing function of the respective deviation parameter, the monotonically increasing function specifying a maximum allowable rectilinear Steiner ratio for a correspondingly ranked net used for the generating of the new layouts of the nets, according to the routing specification;

generating an updated performance parameter for each of the new layouts;

updating the deviation parameter for each of the new layouts with the respective updated performance parameter, the repetitive execution being performed until a first condition or a second condition is fulfilled, the first condition comprising that at least one of the deviation parameters is less than a first threshold value, and the second condition comprising that for a present iteration a performance parameter for a new layout net has an improvement over a respective performance parameter of a previous iteration with the improvement being less than a second threshold value, wherein the deviation parameter of said new layout net is bigger than deviation parameters of other nets for the present iteration;

generating an indicator value for a set of the deviation parameters for one or more most critical nets of the nets, the indicator value being a measure of a difference between a first sum of the deviation parameters of the set of deviation parameters for the one or more most critical nets generated in the previous iteration and a second sum of the deviation parameters of the set of deviation parameters for the one or more most critical nets generated in the present iteration, the present iteration being a next iteration following the previous iteration, the indicator value being equal to the first sum minus the second sum, and the second condition further comprising that the indicator value is less than a third threshold value; and

saving the new layout net as a best possible layout for the integrated circuit; and

based on the saving, fabricating the integrated circuit in accordance with the new layout net.

2. The computer-implemented method of claim 1, wherein each step of the monotonically decreasing step function comprises a corresponding step of the monotonically increasing function.