Technique for distributing routing into superfluous metal section of an integrated circuit

• US 10,452,804 B2
• Filed: 03/02/2017
• Issued: 10/22/2019
• Est. Priority Date: 03/02/2017
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Pelloie, Jean-Luc
• Primary Examiner(s): Doan, Nghia M
• Application Number:
  US15/447,716
• Publication Number:
  US 20180253523A1
• Time in Patent Office: 964 Days
• Field of Search: 716113, 716118-120, 716122, 716126, 716130-135, 716139
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell. Each cell has cell definition data, and the cell definition data of one or more cells is arranged to identify at least one superfluous metal section as being available for routing. During performance of the routing operation, the place and route tool then references the cell definition data of the determined cells so as to take into account, when determining the routing paths, availability of any superfluous metal sections for routing. This can significantly increase the options available to the place and route tool when determining the appropriate routing paths.

Claims

1. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:

receiving input data defining a logical operation of the circuit block;

accessing a cell library providing a plurality of cells that define circuit elements, to determine with reference to the input data the cells to be used to implement the circuit block; and

employing a place and route tool to generate the layout by determining a placement of the determined cells and by performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells;

the cell library providing cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell, each cell having cell definition data, and the cell definition data of one or more cells identifying at least one superfluous metal section as available for routing, wherein said at least one metal layer containing said one or more superfluous metal sections comprises a metal 0 (M0) layer;

during performance of the routing operation, causing the place and route tool to reference the cell definition data of the determined cells so as to take into account, when determining said routing paths, availability of any superfluous metal sections for routing.

2. The method as claimed in claim 1, wherein:

during performance of the routing operation, at least one superfluous metal section is employed to form a portion of a routing path.

3. The method as claimed in claim 2, wherein the superfluous metal sections other than those employed within the routing paths are metal sections that will be left in an electrically floating state in the circuit block.

4. The method as claimed in claim 1, wherein within cells defining an active circuit element, the M0 layer further provides one or more of:

a power supply metal section to connect to a voltage supply;

an input metal section to connect the active circuit element to an input signal routing path;

an output metal section to connect the active circuit element to an output signal routing path; and

an internal metal section to interconnect components of the active circuit element and unavailable to the place and route tool for use as a portion of a routing path.

5. The method as claimed in claim 1, wherein the cells are standard cells, and the place and route tool determines the placement of the determined cells by placing them within a plurality of rows having a common row height.

6. The method as claimed in claim 1, wherein at least one cell whose cell definition data identifies at least one superfluous metal section as available for routing is an inactive cell that has an absence of input and output metal sections.

7. The method as claimed in claim 1, wherein said at least one superfluous metal section identified as available for routing extends over multiple metal layers.

8. The method as claimed in claim 1, further comprising the steps of:

incorporating the layout of the circuit block within a layout of an integrated circuit; and

manufacturing the integrated circuit from the layout of the integrated circuit.

9. A computer program product on a non-transitory storage medium for controlling a computer to perform a method of generating a layout of a circuit block as claimed in claim 1.

10. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:

receiving input data defining a logical operation of the circuit block;

accessing a cell library providing a plurality of cells that define circuit elements, to determine with reference to the input data the cells to be used to implement the circuit block; and

employing a place and route tool to generate the layout by determining a placement of the determined cells and by performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells;

the cell library providing cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell, each cell having cell definition data, and the cell definition data of one or more cells identifying at least one superfluous metal section as available for routing;

during performance of the routing operation, causing the place and route tool to reference the cell definition data of the determined cells so as to take into account, when determining said routing paths, availability of any superfluous metal sections for routing; and

providing the place and route tool with an abstract view of each determined cell as derived from the cell definition data, the abstract view identifying each metal section in said at least one metal layer as one of;

an input/output pin to which a routing path is connectable;

an obstruction that must remain isolated from the routing paths; and

a superfluous metal section available for routing.

11. The method as claimed in claim 10, wherein any superfluous metal section unavailable for routing is identified as an obstruction in said abstract view.

12. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:

receiving input data defining a logical operation of the circuit block;

accessing a cell library providing a plurality of cells that define circuit elements, to determine with reference to the input data the cells to be used to implement the circuit block; and

employing a place and route tool to generate the layout by determining a placement of the determined cells and by performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells;

the cell library providing cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell, each cell having cell definition data, and the cell definition data of one or more cells identifying at least one superfluous metal section as available for routing;

during performance of the routing operation, causing the place and route tool to reference the cell definition data of the determined cells so as to take into account, when determining said routing paths, availability of any superfluous metal sections for routing; and

during the routing operation, when considering employing at least one superfluous metal section to form a portion of a routing path, performing a timing determination operation to take into account a change in signal timing resulting from use of the at least one superfluous metal section.

13. The method as claimed in claim 12, wherein:

the cell library provides, for each cell, associated timing characterisation data assuming any superfluous metal sections are left to electrically float; and

for each cell where at least one superfluous metal section is identified in the cell definition data as available for routing, the cell library provides at least one additional set of timing characterisation data for use by the place and route tool when performing said timing determination operation.

14. The method as claimed in claim 13, wherein:

for each cell where at least one superfluous metal section is identified in the cell definition data as available for routing, the cell library provides one additional set of timing characterisation data for use by the place and route tool when preforming said timing determination operation, said one additional set assuming a worst case timing where all available superfluous metal sections of the cell are used for routing paths.

15. The method as claimed in claim 12, wherein:

the place and route tool performs during said timing determination operation an on-the-fly timing characterisation of an affected cell to take into account a change in signal timing having regard to which of the at least one superfluous metal sections in the affected cell is to form a portion of a routing path.

16. A non-transitory storage medium storing a cell library comprising a plurality of cells that define circuit elements, the cell library providing cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell, each cell having cell definition data, and the cell definition data of one or more cells identifying at least one superfluous metal section as available for routing to a processor-executed place and route tool which is configured to generate a layout for a circuit block by determining a placement of selected cells from the cell library and by referencing the cell definition data of the selected cells to be used to implement a circuit block so as to take into account, when determining routing paths interconnecting the selected cells, availability of any superfluous metal sections for routing, wherein said at least one metal layer containing said one or more superfluous metal sections comprises a metal 0 (M0) layer.