Generating a colored track pattern of non-uniform width from a sparse set of tracks

• US 10,452,806 B1
• Filed: 02/06/2017
• Issued: 10/22/2019
• Est. Priority Date: 02/06/2017
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Rossman, Sabra, Matsunami, Gary, Sharma, Karun, Riley, Steven, Baudhuin, Joshua A.
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US15/425,679
• Time in Patent Office: 988 Days
• Field of Search: 716110, 716126
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.

Claims

1. A method for physically implementing a design for an integrated circuit, comprising:

providing first and second adjacent tracks in a track pattern set of the integrated circuit design, wherein the first and second adjacent tracks comprise a sparse set of tracks that have a metal density below a specified threshold;

presenting a third track between the identified first and second adjacent tracks;

determining whether the first, second and third tracks satisfy design constraints for physically implementing the integrated circuit design; and

if the first, second and third tracks satisfy design constraints, generating a new track pattern set by adding the third track to the track pattern set for the integrated circuit design, the new track pattern set comprising the first, second and third tracks,

wherein the new track pattern set is used as a guide for routing wires during a routing process for physically implementing the integrated circuit design.

2. A method according to claim 1, further comprising creating a geometric representation of the first, second and third tracks before determining whether the first, second and third tracks satisfy design constraints.

3. A method according to claim 1, further comprising assigning colors to the first, second and third tracks in accordance with a color model for physically implementing the integrated circuit design before determining whether the first, second and third tracks satisfy design constraints.

4. A method according to claim 1, wherein determining includes determining a spacing between the first and third tracks in accordance with the design constraints.

5. A method according to claim 1, further comprising optimizing for the track pattern set with respect to the design constraints.

6. A method according to claim 1, wherein presenting the third track includes assigning a width for the third track that is the same as a width for the first track.

7. A method according to claim 1, wherein presenting the third track includes assigning a width for the third track in accordance with a specified density for the track pattern set.

8. A method according to claim 1, wherein presenting the third track includes assigning a width for the third track in accordance with a specified frequency for the track pattern set.

9. A method according to claim 1, wherein presenting the third track includes assigning a width for the third track in accordance with a specified parameter for the track pattern set that is selected by a designer.

10. A method according to claim 1, wherein providing the first and second adjacent tracks includes receiving a selection of the first and second adjacent tracks for use in creating the track pattern set from a designer.

11. A method according to claim 10, further comprising receiving a specified period for the track pattern set from the designer.

12. A method according to claim 1, wherein providing the first and second adjacent tracks includes receiving a selection of a width of the first and second adjacent tracks for use in creating the track pattern set from a designer.

13. A method according to claim 12, further comprising receiving a specified period for the track pattern set from the designer.

14. A method according to claim 1, wherein providing the first and second adjacent tracks includes receiving an identification of a region in the integrated circuit design where no tracks exist between two existing track pattern sets in the integrated circuit design from a designer.

15. A method according to claim 1, wherein providing the first and second adjacent tracks includes receiving an identification of a region in the integrated circuit design where no tracks exist between two existing sets of shapes in the integrated circuit design from a designer.

16. A method according to claim 1, wherein providing the first and second adjacent tracks includes receiving an identification of one or more pins in the integrated circuit design from a designer.

17. A computer readable storage medium having instructions stored thereon which, when executed by a computer, cause the computer to execute a method for physically implementing a design for an integrated circuit, the method comprising:

identifying first and second adjacent tracks of the integrated circuit design;

inserting a third track between the identified first and second adjacent tracks;

determining whether the first, second and third tracks satisfy design constraints for physically implementing the integrated circuit design; and

if the first, second and third tracks satisfy design constraints, adding the third track to a track pattern set for the integrated circuit design, the track pattern set comprising the first, second and third tracks,

wherein the track pattern set is used as a guide for routing wires during a routing process for physically implementing the integrated circuit design.

18. A computer readable storage medium according to claim 17, wherein the method further comprises assigning colors to the first, second and third tracks in accordance with a color model for physically implementing the integrated circuit design before determining whether the first, second and third tracks satisfy design constraints.