Techniques for maintaining atomicity and ordering for pixel shader operations

• US 10,453,168 B2
• Filed: 08/17/2018
• Issued: 10/22/2019
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Hakura, Ziyad, Lum, Eric, Kirkland, Dale, Choquette, Jack, Brown, Patrick R., Uralsky, Yury Y., Bolz, Jeffrey
• Primary Examiner(s): Mazumder, Tapas
• Application Number:
  US15/999,185
• Publication Number:
  US 20180374185A1
• Time in Patent Office: 431 Days
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture

Abstract

A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

Claims

1. A graphics processing pipeline, comprising:

a tile coalescer that receives a first coverage sample and a second coverage sample in an application programming interface order; and

a thread management unit that is coupled to the tile coalescer and causes a first thread group to perform a first operation based on a first dataset that includes the first coverage sample, and causes a second thread group to perform a second operation based on a second dataset that includes the second coverage sample, wherein the first thread group and the second thread group execute on one or more multiprocessors in the application programming interface order;

wherein the tile coalescer and thread management unit are implemented within a processor circuit that includes the one or more multiprocessors.

2. The graphics processing pipeline of claim 1, wherein the tile coalescer generates the first dataset that includes the first coverage sample, and generates the second dataset that includes the second coverage sample.

3. The graphics processing pipeline of claim 2, wherein, when generating the first dataset and the second dataset, the tile coalescer identifies a conflict between the first coverage sample and the second coverage sample.

4. The graphics processing pipeline of claim 3, wherein the tile coalescer identifies the conflict between the first coverage sample and the second coverage sample by determining that the first coverage sample and the second coverage sample both reside at a first X-Y position.

5. The graphics processing pipeline of claim 1, wherein the first operation comprises a read-modify-write operation based on the first dataset, and the second operation comprises a read-modify-write operation based on the second dataset.

6. The graphics processing pipeline of claim 1, wherein the thread management unit assigns a first value to the first thread group when causing the first thread group to perform the first operation, and the thread management unit assigns a second value to the second thread group when causing the second thread group to perform the second operation.

7. The graphics processing pipeline of claim 6, wherein a first thread in the first thread group:

acquires a first number from the thread management unit;

determines that the first value is equal to the first number; and

in response, initiates the first operation, wherein the first thread is executed by the one or more multiprocessors.

8. The graphics processing pipeline of claim 7, wherein a second thread in the second thread group:

acquires a second number from the thread management unit;

determines that the second value is equal to the second number; and

in response, initiates the second operation, wherein the second thread is executed by the one or more multiprocessors.

9. The graphics processing pipeline of claim 8, wherein the thread management unit includes:

a ticket ordering register that stores at least one of the first value and the second value; and

a ticket dispenser register that stores at least one of the first number and the second number.

10. The graphics processing pipeline of claim 1, wherein each of the first operation and the second operation comprises a programmable blending operation.

11. The graphics processing pipeline of claim 1, wherein the first dataset is associated with a first tile corresponding to a first screen space region, and the second dataset is associated with a second tile corresponding to the first screen space region.

12. The graphics processing pipeline of claim 1, wherein each of the one or more multiprocessors includes at least one load-store unit and at least one execution unit that perform operations with pixel data stored in a memory unit.

13. A computer-implemented method, comprising:

receiving a first coverage sample and a second coverage sample in an application programming interface order;

causing a first thread group to perform a first operation based on the first coverage sample; and

causing a second thread group to perform a second operation based on the second coverage sample,

wherein the first thread group and the second thread group execute on one or more multiprocessors in the application programming interface order.

14. The computer-implemented method of claim 13, further comprising generating a first dataset that includes the first coverage sample, and generating a second dataset that includes the second coverage sample, wherein:

causing the first thread group to perform the first operation comprises causing the first thread group to perform the first operation based on the first dataset; and

causing the second thread group to perform the second operation comprises causing the second thread group to perform the second operation based on the second dataset.

15. The computer-implemented method of claim 14, wherein generating the first dataset and the second dataset comprises identifying a conflict between the first coverage sample and the second coverage sample.

16. The computer-implemented method of claim 15, wherein identifying the conflict between the first coverage sample and the second coverage sample comprises determining that the first coverage sample and the second coverage sample both reside at a first X-Y position.

17. The computer-implemented method of claim 13, wherein:

causing the first thread group to perform the first operation comprises causing the first thread group to perform the first operation based on a first dataset,

causing the second thread group to perform the second operation comprises causing the second thread group to perform the second operation based on a second dataset,

the first operation comprises a read-modify-write operation based on the first dataset, and

the second operation comprises a read-modify-write operation based on the second dataset.

18. The computer-implemented method of claim 13, wherein causing the first thread group to perform the first operation comprises assigning a first value to the first thread group, and causing the second thread group to perform the second operation comprises assigning a second value to the second thread group.

19. The computer-implemented method of claim 18, further comprising:

acquiring a first number from a thread management unit;

determining that the first value is equal to the first number; and

in response, initiating the first operation.

20. The computer-implemented method of claim 19, further comprising:

acquiring a second number from the thread management unit;

determining that the second value is equal to the second number; and

in response, initiating the second operation.

21. The computer-implemented method of claim 20, wherein the thread management unit includes:

a ticket ordering register that stores at least one of the first value and the second value; and

a ticket dispenser register that stores at least one of the first number and the second number.

22. The computer-implemented method of claim 13, wherein each of the first operation and the second operation comprises a programmable blending operation.

23. The computer-implemented method of claim 13, wherein:

causing the first thread group to perform the first operation comprises causing the first thread group to perform the first operation based on a first dataset,

causing the second thread group to perform the second operation comprises causing the second thread group to perform the second operation based on a second dataset,

the first dataset is associated with a first tile corresponding to a first screen space region, and

the second dataset is associated with a second tile corresponding to the first screen space region.

24. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform the steps of:

receiving a first coverage sample in an application programming interface order;

causing a first thread group to perform a first operation based on a first dataset that includes the first coverage sample,

wherein the first thread group executes on one or more multiprocessors in the application programming interface order.

25. The non-transitory computer-readable medium of claim 24, further comprising:

receiving a second coverage sample in the application programming interface order;

causing a second thread group to perform a second operation based on a second dataset that includes the second coverage sample,

wherein the second thread group executes on the one or more multiprocessors in the application programming interface order.