High capacity memory system using controller component

• US 10,453,517 B2
• Filed: 04/10/2017
• Issued: 10/22/2019
• Est. Priority Date: 11/11/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh, Best, Scott C.
• Primary Examiner(s): Mamo, Elias
• Application Number:
  US15/483,817
• Publication Number:
  US 20170330610A1
• Time in Patent Office: 925 Days
• Field of Search: None
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Claims

1. A memory controller component comprising:

a first mode; and

a second mode, wherein the memory controller component, in the first mode, is to communicate with a first memory module over a first type of memory channel comprising a first plurality of data-links that are multi-drop data-links shared with all other memory modules connected to the memory controller component to which the first memory module is connected, wherein the memory controller component, in the second mode, is to communicate with a second memory module over a second type of memory channel comprising a second plurality of data-links that are point-to-point data links and some of the second plurality of data-links do not connect to all other memory modules connected to the memory controller component to which the second memory module is connected.

2. The memory controller component of claim 1, wherein the memory controller component is integrated in a processor.

3. The memory controller component of claim 1, wherein the memory controller component is disposed on a motherboard substrate comprising the multi-drop data-links and at least the first memory module, and wherein the memory controller component is to operate in the first mode.

4. The memory controller component of claim 1, wherein the memory controller component is disposed on a motherboard substrate comprising the point-to-point data-links and at least the second memory module, and wherein the memory controller component is to operate in the second mode.

5. The memory controller component of claim 3, wherein the first memory module comprises:

a plurality of device sites; and

a data buffer component coupled to the plurality of device sites and the memory controller component, wherein the data buffer component comprises a first mode corresponding to the first mode of the memory controller component and a second mode corresponding to the second mode of the memory controller component, wherein the data buffer component is to operate in the first mode when the first memory module is inserted onto the first type of memory channel with the multi-drop data-links.

6. The memory controller component of claim 4, wherein the first memory module further comprises:

a plurality of device sites;

at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites of the plurality of device sites;

nine data buffer components coupled to the at least eighteen DRAM devices and the memory controller component, each of the nine data buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine data buffer components each comprise a first mode corresponding to the first mode of the memory controller component and a second mode corresponding to the second mode of the memory controller component, and wherein the nine data buffer components each operate in the first mode when the first memory module is inserted onto the first type of memory channel with the multi-drop data-links; and

a command and address (CA) buffer component coupled to the at least eighteen DRAM devices and the memory controller component.

7. A device comprising

a memory controller component having:

a first mode in which the memory controller component initializes a first memory in which data-links use a multi-drop topology that connects all module sockets of a motherboard substrate to the memory controller component; and

a second mode in which the memory controller component initializes a second memory in which some data-links do not connect to all module sockets of a motherboard substrate.

8. The device of claim 7, wherein the data-links of the second memory system use a point-to-point topology.

9. The device of claim 7, wherein the device is disposed on a motherboard substrate comprising at least three module sockets.

10. The device of claim 9, wherein the motherboard substrate comprises the data-links that use the multi-drop topology.

11. The system device of claim 9, wherein the motherboard substrate comprises data-links that use a point-to-point topology.

12. The device of claim 9, wherein the motherboard substrate comprises a private link coupled between a first module socket and a second module socket of the at least three module sockets.

13. The device of claim 9, wherein the memory controller component is to access data stored at a first memory module inserted in a first module socket of the at least three module sockets, wherein the data, when accessed by the memory controller component, passes in a first link-connection of a second memory module and out a second link-connection of the second memory module, wherein the second memory module is inserted in a second module socket of the at least three memory module sockets.

14. The device of claim 9, wherein the memory controller component is to access data stored at a first memory module inserted in a first module socket of the at least three module sockets, wherein the data, when accessed by the memory controller component, passes through one of the following of a second memory module:

a wire connection;

a pass-transistor;

an unclocked receiver-transmitter pair;

or

a clocked receiver-transmitter pair.

15. The device of claim 9, wherein the memory controller component is to access first data stored at a single memory module in response to a first command to a first address, and wherein the memory controller component is to access second data stored at a plurality of memory modules in response to a second command to a second address.

16. The device of claim 9, wherein the memory controller component is to:

communicate with a first memory module that is inserted into a first module socket of the at least three module sockets; and

communicate with a second memory module that is inserted into a second module socket of the at least three module sockets, wherein the first memory module is to share information regarding a selection of ranks to be accessed with the second memory module.

17. The device of claim 9, wherein the memory controller component is to:

communicate with a first memory module that is inserted into a first module socket of the at least three module sockets; and

communicate with a second memory module that is inserted into a second module socket of the at least three module sockets, wherein the first memory module is to share information regarding how data is to be bypassed through the second module with the second module.

18. The device of claim 9, wherein the memory controller component is to:

communicate with a first memory module that is inserted into a first module socket of the at least three module sockets; and

communicate with a second memory module that is inserted into a second module socket of the at least three module sockets, wherein the first memory module is to compensate for a delay when data is bypassed through the second memory module.

19. The device of claim 9, wherein the memory controller component is to:

communicate with a first memory module that is inserted into a first module socket of the at least three module sockets; and

communicate with a second memory module that is inserted into a second module socket of the at least three module sockets, wherein the memory controller component is to compensate for a delay when data is bypassed through the second memory module.

20. An integrated circuit comprising:

a memory controller,

wherein the memory controller, when the integrated circuit is inserted into a socket of a first motherboard substrate, is to communicate with a first plurality of memory modules disposed in module sockets of the first motherboard substrate using multi-drop data-links which are shared with all of the first plurality of memory modules connected to the memory controller, and

wherein the memory controller, when the integrated circuit is inserted into a socket of a second motherboard substrate, is to communicate with a second plurality of memory modules disposed in module sockets of the second motherboard substrate using point-to-point data links and some of the point-to-point data-links do not connect to all of the second plurality of memory modules connected to the memory controller component.