Preservation circuit and methods to maintain values representing data in one or more layers of memory

• US 10,453,525 B2
• Filed: 11/27/2017
• Issued: 10/22/2019
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Chevallier, Christophe, Norman, Robert
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/823,270
• Publication Number:
  US 20180182454A1
• Time in Patent Office: 694 Days
• Field of Search: 365148, 365158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Claims

1. A memory device comprising:

a memory bus;

a plurality of memory chips coupled to the memory bus, wherein each of the plurality of memory chips comprises at least one layer of memory cells to store logic states;

a trigger circuit coupled to the memory bus, the trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the memory device from a host computing system coupled to the memory device; and

a shared preservation circuit coupled to the memory bus, wherein the shared preservation circuit is configured to perform preservation operations on each of the plurality of memory chips to preserve and restore the logic states in response to the trigger signal.

2. The memory device of claim 1, wherein at least one of the plurality of memory chips comprises two or more layers of memory cells.

3. The memory device of claim 1, wherein the at least one layer of memory cells comprises a plurality of two-terminal non-volatile memory cells configured in at least one two-terminal cross-point array.

4. The memory device of claim 1, wherein the trigger circuit to detect a change in power supplied to the memory device as the triggering event.

5. The memory device of claim 1, wherein the memory cells to store the logic states as separate resistive values determined as a function of a voltage.

6. The memory device of claim 5, wherein the shared preservation circuit comprises at least one buffer configured to store the logic states of the memory cells during the preservation operations.

7. The memory device of claim 6, wherein to preserve and restore a logic state of a first memory cell, the shared preservation circuit to:

apply a read voltage to the first memory cell to determine a resistive value;

store an indication of the resistive value in the at least one buffer; and

apply a write voltage to the first memory cell to store the resistive value in the first memory cell.

8. An integrated circuit comprising:

a memory bus;

a first memory device coupled to the memory bus;

a second memory device coupled to the memory bus, wherein each of the first and second memory devices comprises at least one layer of memory elements to store logic states;

a trigger circuit coupled to the memory bus, the trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the first and second memory devices from a host computing system coupled to the first and second memory devices; and

a shared preservation circuit coupled to the memory bus, wherein the shared preservation circuit is configured to perform preservation operations on the first and second memory devices to preserve and restore the logic states in response to the trigger signal.

9. The integrated circuit of claim 8, wherein at least one of the first and second memory devices comprises two or more layers of memory elements.

10. The integrated circuit of claim 8, wherein the at least one layer of memory elements comprises a plurality of two-terminal non-volatile memory elements configured in at least one two-terminal cross-point array.

11. The integrated circuit of claim 8, wherein the trigger circuit to detect a change in power supplied to the integrated circuit as the triggering event.

12. The integrated circuit of claim 8, wherein the memory elements to store the logic states as separate resistive values determined as a function of a voltage.

13. The integrated circuit of claim 12, wherein the shared preservation circuit comprises at least one buffer configured to store the logic states of the memory elements during the preservation operations.

14. The integrated circuit of claim 13, wherein to preserve and restore a logic state of a first memory element, the shared preservation circuit to:

apply a read voltage to the first memory element to determine a resistive value;

store an indication of the resistive value in the at least one buffer; and

apply a write voltage to the first memory element to store the resistive value in the first memory element.

15. A system comprising:

a host device; and

a memory component coupled to the host device via a memory bus, the memory component comprising;

a plurality of memory chips, wherein each of the plurality of memory chips comprises at least one layer of memory cells to store logic states;

a trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the memory component from the host device; and

a shared preservation circuit configured to perform preservation operations on each of the plurality of memory chips to preserve and restore the logic states in response to the trigger signal.

16. The system of claim 15, wherein at least one of the plurality of memory chips comprises two or more layers of memory cells each comprising a plurality of two-terminal non-volatile memory cells configured in at least one two-terminal cross-point array.

17. The system of claim 15, wherein the trigger circuit to detect a change in power supplied to the memory component as the triggering event.

18. The system of claim 15, wherein the memory cells to store the logic states as separate resistive values determined as a function of a voltage.