Preservation circuit and methods to maintain values representing data in one or more layers of memory
First Claim
1. A memory device comprising:
- a memory bus;
a plurality of memory chips coupled to the memory bus, wherein each of the plurality of memory chips comprises at least one layer of memory cells to store logic states;
a trigger circuit coupled to the memory bus, the trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the memory device from a host computing system coupled to the memory device; and
a shared preservation circuit coupled to the memory bus, wherein the shared preservation circuit is configured to perform preservation operations on each of the plurality of memory chips to preserve and restore the logic states in response to the trigger signal.
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Accused Products
Abstract
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
143 Citations
18 Claims
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1. A memory device comprising:
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a memory bus; a plurality of memory chips coupled to the memory bus, wherein each of the plurality of memory chips comprises at least one layer of memory cells to store logic states; a trigger circuit coupled to the memory bus, the trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the memory device from a host computing system coupled to the memory device; and a shared preservation circuit coupled to the memory bus, wherein the shared preservation circuit is configured to perform preservation operations on each of the plurality of memory chips to preserve and restore the logic states in response to the trigger signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit comprising:
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a memory bus; a first memory device coupled to the memory bus; a second memory device coupled to the memory bus, wherein each of the first and second memory devices comprises at least one layer of memory elements to store logic states; a trigger circuit coupled to the memory bus, the trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the first and second memory devices from a host computing system coupled to the first and second memory devices; and a shared preservation circuit coupled to the memory bus, wherein the shared preservation circuit is configured to perform preservation operations on the first and second memory devices to preserve and restore the logic states in response to the trigger signal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a host device; and a memory component coupled to the host device via a memory bus, the memory component comprising; a plurality of memory chips, wherein each of the plurality of memory chips comprises at least one layer of memory cells to store logic states; a trigger circuit to detect a triggering event and generate a trigger signal, the triggering event comprising an application of power to the memory component from the host device; and a shared preservation circuit configured to perform preservation operations on each of the plurality of memory chips to preserve and restore the logic states in response to the trigger signal. - View Dependent Claims (16, 17, 18)
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Specification