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Distributed cascode current source for RRAM set current limitation

  • US 10,453,526 B2
  • Filed: 08/16/2018
  • Issued: 10/22/2019
  • Est. Priority Date: 02/26/2014
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory cell array comprising a plurality of columns, wherein each column comprises;

    a source line,a plurality of memory cells, wherein each of the memory cells comprises a memory element coupled to the source line through a word line select transistor, anda bit line, wherein the bit line runs parallel to the source line;

    a column selector coupled to the source lines;

    a current limiting device coupled between the source lines and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cells; and

    a diode configured stack of transistors, wherein a first transistor of the stack is selectively coupled to one of the gates of the word line select transistors, and a second transistor of the stack is coupled to the current limiting device.

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