Distributed cascode current source for RRAM set current limitation

• US 10,453,526 B2
• Filed: 08/16/2018
• Issued: 10/22/2019
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Hefei Reliance Memory Limited
• Original Assignee: Hefei Reliance Memory Limited
• Inventors: Bateman, Bruce Lynn
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US16/103,967
• Publication Number:
  US 20180358092A1
• Time in Patent Office: 432 Days
• Field of Search: 365148
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Claims

1. An apparatus, comprising:

a memory cell array comprising a plurality of columns, wherein each column comprises;

a source line,

a plurality of memory cells, wherein each of the memory cells comprises a memory element coupled to the source line through a word line select transistor, and

a bit line, wherein the bit line runs parallel to the source line;

a column selector coupled to the source lines;

a current limiting device coupled between the source lines and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cells; and

a diode configured stack of transistors, wherein a first transistor of the stack is selectively coupled to one of the gates of the word line select transistors, and a second transistor of the stack is coupled to the current limiting device.

2. The apparatus of claim 1, further comprising an array control circuitry coupled to the memory cell array, the array control circuitry configured to control the constant current mode and supply an associated select bias voltage to the word line select transistors.

3. The apparatus of claim 1, wherein the current limiting device comprises a pull-down transistor biased in saturation.

4. The apparatus of claim 1, wherein the diode configured stack of transistors comprises a diode configured stack of differently sized transistors.

5. The apparatus of claim 4, wherein a first size of the word line select transistors is less than a second size of the pull-down transistor.

6. An apparatus, comprising:

a memory cell array comprising a plurality of columns, wherein each column comprises;

a source line,

a plurality of memory cells, wherein each of the memory cells comprises a memory element coupled to the source line through a word line select transistor,

a bit line, wherein the bit line runs parallel to the source line, and

a current limiting device coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cells of the column;

a column selector coupled to the source lines; and

a diode configured stack of transistors, wherein a first transistor of the stack is selectively coupled to one of the gates of the word line select transistors, and a second transistor of the stack is coupled to the current limiting device.

7. The apparatus of claim 6, further comprising an array control circuitry coupled to the memory cell array, the array control circuitry configured to control the constant current mode and supply an associated select bias voltage to the word line select transistors.

8. The apparatus of claim 6, wherein each of the current limiting devices comprises a pull-down transistor biased in saturation.

9. The apparatus of claim 6, wherein the diode configured stack of transistors comprises a diode configured stack of differently sized transistors.

10. The apparatus of claim 9, wherein a first size of the word line select transistors is less than a second size of the pull-down transistors.

11. An apparatus, comprising:

a memory cell array comprising a plurality of rows, wherein each row comprises;

a source line,

a plurality of memory cells, wherein each of the memory cells comprises a memory element coupled to the source line through a word line select transistor,

a word line, wherein the word line runs parallel to the source line, and

a current limiting device coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cells of the row;

a row selector coupled to the source lines; and

a diode configured stack of transistors, wherein a first transistor of the stack is selectively coupled to one of the gates of the word line select transistors, and a second transistor of the stack is coupled to the current limiting device.

12. The apparatus of claim 11, further comprising an array control circuitry coupled to the memory cell array, the array control circuitry configured to control the constant current mode and supply an associated select bias voltage to the word line select transistors.

13. The apparatus of claim 11, wherein each of the current limiting devices comprises a pull-down transistor biased in saturation.

14. The apparatus of claim 11, wherein the diode configured stack of transistors comprises a diode configured stack of differently sized transistors.

15. The apparatus of claim 14, wherein a first size of the word line select transistors is less than a second size of the pull-down transistors.