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Memory devices with distributed block select for a vertical string driver tile architecture

  • US 10,453,533 B2
  • Filed: 11/17/2017
  • Issued: 10/22/2019
  • Est. Priority Date: 11/17/2017
  • Status: Active Grant
First Claim
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1. A memory device having a tile architecture, the memory device comprising:

  • a first tile pair including a first tile, a second tile, a first vertical string driver positioned between the first tile and the second tile, and a first page buffer region that is greater than 50% of area for the first tile pair, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry; and

    a second tile pair including a third tile, a fourth tile, a second vertical string driver positioned between the third tile and the fourth tile, a second page buffer region that is greater than 50% of area for the second tile pair, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry,wherein the first portion, the second portion, the third portion, and the fourth portion of the distributed block select circuitry are each coupled to the first vertical string driver and the second vertical string driver.

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