Memory devices with distributed block select for a vertical string driver tile architecture
First Claim
1. A memory device having a tile architecture, the memory device comprising:
- a first tile pair including a first tile, a second tile, a first vertical string driver positioned between the first tile and the second tile, and a first page buffer region that is greater than 50% of area for the first tile pair, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry; and
a second tile pair including a third tile, a fourth tile, a second vertical string driver positioned between the third tile and the fourth tile, a second page buffer region that is greater than 50% of area for the second tile pair, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry,wherein the first portion, the second portion, the third portion, and the fourth portion of the distributed block select circuitry are each coupled to the first vertical string driver and the second vertical string driver.
5 Assignments
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Accused Products
Abstract
Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.
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Citations
16 Claims
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1. A memory device having a tile architecture, the memory device comprising:
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a first tile pair including a first tile, a second tile, a first vertical string driver positioned between the first tile and the second tile, and a first page buffer region that is greater than 50% of area for the first tile pair, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry; and a second tile pair including a third tile, a fourth tile, a second vertical string driver positioned between the third tile and the fourth tile, a second page buffer region that is greater than 50% of area for the second tile pair, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry, wherein the first portion, the second portion, the third portion, and the fourth portion of the distributed block select circuitry are each coupled to the first vertical string driver and the second vertical string driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device having a tile architecture, comprising:
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a memory array; and a CMOS under array (CUA) region including; at least some tile regions including portions of a total amount of block select circuitry distributed throughout the CUA region, each portion of the portions of the block select circuitry offset from at least one other portion of the portions of the block select circuitry; vertical string drivers located outside of the memory array, each vertical string driver of the vertical string drivers coupled to each portion of the block select circuitry located within different tile regions; and page buffer circuitry coupled with the memory array. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification