Apparatus and methods including establishing a negative body potential in a memory cell

• US 10,453,538 B2
• Filed: 07/16/2018
• Issued: 10/22/2019
• Est. Priority Date: 11/14/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji, Hawes, Mark, Tanzawa, Toru, Binfet, Jeremy
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/035,933
• Publication Number:
  US 20180322930A1
• Time in Patent Office: 463 Days
• Field of Search: 36518501-18533
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

Claims

1. A method of operating an apparatus, comprising:

advancing a timer; and

establishing a negative potential in a body of a memory cell of a memory in response to a value of the timer having a desired value.

2. The method of claim 1, wherein the timer is external to the memory, and wherein establishing the negative potential in the body of the memory cell is performed in response to a command received by the memory from a device external to the memory that is in communication with the timer.

3. The method of claim 1, wherein the timer comprises a counter responsive to a clock signal, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to a count value of the counter having the desired value.

4. The method of claim 3, further comprising:

resetting the counter to an initial value after the count value has the desired value.

5. The method of claim 3, further comprising:

modifying the desired value of the count value in response to a temperature sensor indicating a temperature higher than a predefined upper threshold or lower than a predefined lower threshold.

6. The method of claim 1, wherein the timer is configured to periodically toggle a logic level of an output signal from a first logic level to a second logic level at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having the second logic level.

7. The method of claim 6, further comprising:

increasing a length of the intervals in response to a temperature sensor indicating a temperature higher than a predefined upper threshold; and

decreasing a length of the intervals in response to a temperature sensor indicating a temperature lower than a predefined lower threshold.

8. The method of claim 1, wherein establishing the negative potential in the body of the memory cell comprises applying a negative voltage level to a source connected to the body of the memory cell.

9. The method of claim 1, wherein the memory cell is a particular memory cell of a string of series-connected memory cells, and wherein establishing the negative potential in the body of the memory cell comprises applying a same positive voltage level to each access line of a plurality of access lines, where each access line of the plurality of access lines is connected to a respective memory cell of the string of series-connected memory cells.

10. The method of claim 1, further comprising initiating a sensing operation on the memory cell while the body of the memory cell has the negative potential.

11. The method of claim 1, wherein the timer is configured to toggle a logic level of an output signal at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having a particular logic level.

12. The method of claim 11, further comprising:

modifying a length of the intervals in response to an indication of temperature.