Memory device and method of operating the same

• US 10,453,542 B2
• Filed: 05/11/2018
• Issued: 10/22/2019
• Est. Priority Date: 07/26/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Hae Soo
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US15/977,410
• Publication Number:
  US 20190035481A1
• Time in Patent Office: 529 Days
• Field of Search: 36518519, 36518522, 365226, 365 491
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

Provided herein may be a method of operating a memory device. The method may include applying an erase voltage to a memory block. The method may include performing an erase verify operation on the memory block. The method may include performing a first blind program operation based on a result of the erase verify operation.

Claims

1. A method of operating a memory device comprising:

applying an erase voltage to a memory block;

performing an erase verify operation on the memory block to determine whether threshold voltages of memory cells included in the memory block have reached the erase state;

performing a first blind program operation on the memory block if the erase verify operation fails; and

applying a changed erase voltage which has a higher voltage level than the erase voltage to the memory block.

2. The method according to claim 1, wherein the first blind program operation is performed by simultaneously applying a first blind program voltage to a plurality of word lines coupled to the memory block.

3. The method according to claim 1, further comprising, before the applying of the erase voltage, performing a second blind program operation on the memory block.

4. The method according to claim 3, wherein the second blind program operation is performed regardless of whether a program operation has been performed on the memory block.

5. The method according to claim 3, wherein performing the second blind program operation on the memory block includes increasing the threshold voltages of the memory cells.

6. The method according to claim 2, further comprising, after the first blind program operation has been performed:

applying a changed erase voltage having a higher voltage level than the erase voltage to the memory block; and

performing the first blind program operation using a changed first blind program voltage having a higher voltage level than the first blind voltage.

7. The method according to claim 2, further comprising, after applying the changed erase voltage, performing the first blind program operation using the first blind program voltage again.

8. The method according to claim 2, further comprising, after the first blind program operation has been performed:

applying a changed erase voltage having a higher voltage level than the erase voltage to the memory block; and

performing the first blind program operation using a decreased first blind program voltage having a lower voltage level than the first blind voltage.

9. The method according to claim 1, further comprising performing a second blind program operation when the erase verify operation passes.

10. The method according to claim 9,

wherein the second blind program operation includes a plurality of blind program loops, and

wherein each of the blind program loops comprises a second blind program voltage application operation and a blind program verify operation.

11. The method according to claim 10, wherein the blind program verify operation comprises determining that the second blind program operation has passed, when the number of strings that are determined to be turned off is a predetermined value or more.

12. The method according to claim 11, wherein the blind program verify operation is successively performed on memory cells coupled to an even bit line and memory cells coupled to an odd bit line.

13. A method of operating a memory device comprising:

applying an erase voltage to a memory block;

performing an erase verify operation on the memory block to determine whether threshold voltages of memory cells included in the memory block have reached the erase state; and

performing a first blind program operation on the memory block if it is determined that the erase verify operation fails according to an erase count value of the memory block,

wherein the first blind program operation is performed when the erase count value is greater than a predetermined first threshold value.

14. The method according to claim 13, further comprising, before the applying of the erase voltage, performing a second blind program operation on the memory block when the erase count value is greater than a predetermined second threshold value.

15. The method according to claim 13, further comprising performing a second blind program operation on the memory block if the erase verify operation passes, and when the erase count value is greater than a predetermined second threshold value.

16. A semiconductor memory device comprising:

a memory block including a plurality memory cells;

a peripheral circuit configured to perform an erase operation on the memory block; and

a control logic configured to control the peripheral circuit to apply an erase voltage to the memory block, to perform an erase verify operation on the memory block to determine whether threshold voltages of memory cells included in the memory block have reached the erase state, to perform a first blind program operation on the memory block if the erase verify operation fails and to apply a changed erase voltage having a higher voltage than the erase voltage to the memory block after the first blind program operation has been performed.

17. The semiconductor memory device of claim 16,

wherein the control logic is configured to control the peripheral circuit to perform the first blind program operation by simultaneously applying a first blind program voltage to a plurality of word lines coupled to the memory block.

18. The semiconductor memory device of claim 16,

wherein the control logic is configured to control the peripheral circuit to perform a second blind program operation on the memory block before the erase voltage is applied to the memory block.

19. The semiconductor memory device of claim 18,

wherein the control logic is configured to control the peripheral circuit to perform the second blind program operation regardless of whether a program operation has been performed on the memory block.

20. The semiconductor memory device of claim 18,

wherein the second blind program operation is performed on the memory block to increase the threshold voltages of the memory cells.

21. The semiconductor memory device of claim 17,

wherein the control logic is configured to control the peripheral circuit to perform the first blind program operation using a changed first blind program voltage having a different voltage level from the first blind voltage.