Multilayer ceramic capacitor

• US 10,453,610 B2
• Filed: 10/10/2017
• Issued: 10/22/2019
• Est. Priority Date: 10/11/2016
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Fukunaga, Daiki
• Primary Examiner(s): Wiese, Noah S
• Application Number:
  US15/728,568
• Publication Number:
  US 20180102217A1
• Time in Patent Office: 742 Days
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/1227 based on alkaline earth titanates
• CPC Class Codes: H01G 4/224 Housing; Encapsulation
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/2325 characterised by the material of the terminals
• CPC Class Codes: H01G 4/248 the terminals embracing or surrounding the capacitive element, e.g. caps H01G4/252 takes precedence
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence

Abstract

A multilayer ceramic capacitor with improved moisture resistance includes a laminate in which dielectric ceramic layers and internal electrodes are alternately stacked, and a pair of external electrodes provided on corresponding outer portions of the laminate. Each dielectric ceramic layer positioned between the internal electrodes, a first region positioned between the internal electrode and a first side surface in a width direction, and a second region positioned between the internal electrode and a second side surface, contains a perovskite compound containing Ba and Ti, and at least one element selected from a group consisting of Ba, Mg, Mn and a rare-earth element. Relationships S1<Sa and S2<Sa are satisfied, where mole ratios of the at least one element to Ti of the dielectric ceramic layer, the first region, and the second region, are respectively designated as Sa, S1, and S2, respectively.

Claims

1. A multilayer ceramic capacitor comprising:

a laminate including a plurality of dielectric layers and internal electrodes that are alternately stacked with each other; and

a pair of external electrodes each of which is provided on a surface of the laminate to be electrically connected to the internal electrodes extended to the surface of the laminate;

wherein

the laminate includes;

a first principal surface and a second principal surface, facing each other in a thickness direction being a lamination direction of the dielectric layers and the internal electrodes;

a first end surface and a second end surface, facing each other in a lengthwise direction being a direction in which the pair of external electrodes faces each other, and being provided with the corresponding external electrodes; and

a first side surface and a second side surface, facing each other in a width direction perpendicular or substantially perpendicular to the thickness direction and the lengthwise direction;

wherein

the dielectric layers, a first region positioned between the internal electrode and the first side surface in the width direction, and a second region positioned between the internal electrode and the second side surface in the width direction, in portions of the laminate, include a perovskite compound containing Ba and Ti, and at least one element selected from a group consisting of Ba, Mg, Mn and a rare-earth element; and

relationships S1<

Sa, and S2<

Sa are satisfied where a mole ratio of the at least one element to the Ti in the first region, a mole ratio of the at least one element to the Ti in the second region, and a mole ratio of the at least one element to the Ti in one of the plurality of dielectric layer positioned between the internal electrodes, are S1, S2, and Sa, respectively.

2. The multilayer ceramic capacitor according to claim 1, wherein

each of a third region positioned between one of the plurality of dielectric layers and the first side surface in the width direction, and a fourth region positioned between one of the plurality of dielectric layers and the second side surface in the width direction, in the portions of the laminate, includes a perovskite compound containing Ba and Ti, and at least one element selected from a group consisting of Ba, Mg, Mn and a rare-earth element;

and

relationships SS1<

Sa and SS2<

Sa are satisfied, where a mole ratio of the at least one element to the Ti in the third region, and a mole ratio of the at least one element to the Ti in the fourth region, are SS1 and SS2, respectively.

3. The multilayer ceramic capacitor according to claim 2, wherein

a relationship S1<

SS1<

Sa is satisfied; and

a relationship S2<

SS2<

Sa is satisfied.

4. The multilayer ceramic capacitor according to claim 1, wherein a dimension of the first region in the width direction and a dimension of the second region in the width direction, is not less than about 2 μ

m and not more than about 30 μ

m.

5. The multilayer ceramic capacitor according to claim 1, wherein the one of the plurality of dielectric layers has a thickness of not less than about 0.4 μ

m and not more than about 0.8 μ

m.

6. The multilayer ceramic capacitor according to claim 1, wherein the laminate is rectangular or substantially rectangular parallelepiped in shape.

7. The multilayer ceramic capacitor according to claim 1, wherein the laminate includes rounded corners and rounded ridge line portions.

8. The multilayer ceramic capacitor according to claim 1, wherein an outer one of the plurality of dielectric layers has a thickness of about 10 μ

m or more.

9. The multilayer ceramic capacitor according to claim 1, wherein a number of the plurality of dielectric layers included in the laminate is not less than 150 and not more than 200.

10. The multilayer ceramic capacitor according to claim 1, wherein ones of the plurality of dielectric layers included in the first region and the second region have a greater density than ones of the plurality of dielectric layers positioned outside of the first region and the second region.

11. The multilayer ceramic capacitor according to claim 2, wherein ones of the plurality of dielectric layers included in the third region and the fourth region have a greater density than ones of the plurality of dielectric layers positioned outside of the third region and the fourth region.

12. The multilayer ceramic capacitor according to claim 1, wherein the internal electrodes include dielectric grains.

13. The multilayer ceramic capacitor according to claim 1, wherein each of the internal electrodes has a thickness of not less than about 0.4 μ

m and not more than about 0.7 μ

m.

14. The multilayer ceramic capacitor according to claim 1, wherein a number of the internal electrodes is not less than 150 and not more than 200.

15. The multilayer ceramic capacitor according to claim 1, wherein each of the internal electrodes has a coverage ratio of not less than 60% and not more than 80%.

16. The multilayer ceramic capacitor according to claim 1, wherein the laminate includes longitudinal gaps defined by regions extending from leading ends of the internal electrodes on opposite sides of extended electrode portions to the first and second end surfaces of the laminate.

17. The multilayer ceramic capacitor according to claim 16, wherein a dimension each of the longitudinal gaps is not less than about 10 μ

m and not more than about 40 μ

m.

18. The multilayer ceramic capacitor according to claim 1, wherein each of the pair of external electrodes includes a base electrode layer on the laminate and a plating layer on the base electrode layer.

19. The multilayer ceramic capacitor according to claim 18, wherein the base electrode layer includes at least one of a baked electrode layer, a resin electrode layer, and a thin film electrode layer.

20. The multilayer ceramic capacitor according to claim 18, wherein the plating layer includes an Ni plating layer and an Sn plating layer.