Forming semiconductor device by providing an amorphous silicon core with a hard mask layer

• US 10,453,685 B2
• Filed: 03/31/2017
• Issued: 10/22/2019
• Est. Priority Date: 03/31/2017
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Houben, Kelly, Van Aerde, Steven R. A., Stokhof, Maarten, Jongbloed, Bert, Pierreux, Dieter, Knaepen, Werner
• Primary Examiner(s): Bachner, Robert G
• Application Number:
  US15/476,752
• Publication Number:
  US 20180286679A1
• Time in Patent Office: 935 Days
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

Claims

1. A method of forming a semiconductor device comprising:

patterning a substrate, wherein patterning the substrate comprises;

providing a lower amorphous silicon layer on the substrate, wherein the lower amorphous silicon layer is provided with an anti-crystallization dopant;

forming an upper hard mask layer above the lower silicon layer;

forming openings in the upper hard mask layer, the openings exposing portions of the lower amorphous silicon layer;

anisotropically etching the lower amorphous silicon layer through the openings in the upper hard mask layer to define a patterned lower amorphous silicon layer;

removing the upper hard mask layer;

depositing a conformal layer on the patterned lower amorphous silicon layer;

anisotropically etching the second conformal layer to leave vertical portions of the second conformal layer along sidewalls of the patterned lower amorphous silicon layer; and

removing the lower amorphous silicon layer while retaining the vertical portions of the second conformal layer.

2. The method according to claim 1, wherein the upper hard mask layer comprises silicon and nitrogen.

3. The method according to claim 1 or 2, wherein a concentration of the dopant is less than 25 at %, wherein the concentration is sufficient to maintain the lower amorphous silicon layer in an amorphous state during patterning the substrate.

4. The method according to claim 1, wherein the amorphous silicon layer is formed by depositing a silicon-comprising reactant.

5. The method according to claim 4, wherein the silicon-comprising reactant is selected from the group consisting of silanes and halosilanes.

6. The method according to claim 4, wherein the silicon-comprising reactant comprises an organosilane and the anti-crystallization dopant is one or both of carbon and hydrogen from the organosilane remaining within the lower amorphous silicon layer after deposition.

7. The method according to claim 4, wherein the silicon-comprising reactant comprises Si_nH_(2n+2) wherein n is at least 2, further comprising:

depositing silicon from the silicon-comprising reactant at a deposition temperature below 500°

C., wherein the anti-crystallization dopant comprises hydrogen from the Si_nH_(2n+2).

8. The method according to claim 1, wherein the anti-crystallization dopant comprises one or more of oxygen, hydrogen, nitrogen, carbon, and sulfur.

9. The method according to claim 8, wherein providing a lower amorphous silicon layer comprises using N₂O as an oxygen source during deposition of the amorphous silicon layer.

10. The method according to claim 8, wherein the anti-crystallization dopant is provided by using an anti-crystallization dopant comprising carbon during deposition of the amorphous silicon layer.

11. The method according to claim 8, wherein the anti-crystallization dopant is provided by co-flowing a N-precursor comprising nitrogen during depositing silicon from a silicon-comprising reactant to form the lower amorphous silicon layer.

12. The method according to claim 8, wherein the anti-crystallization dopant is provided by co-flowing a S-precursor comprising Sulphur during depositing silicon from a silicon-comprising reactant to form the lower amorphous silicon layer.

13. The method according to claim 1, wherein forming the upper hard mask layer on the lower amorphous silicon layer comprises heating the substrate to a temperature above 550°

C., wherein the lower amorphous silicon layer with the anti-crystallization dopant remains amorphous during heating the substrate.

14. The method according to claim 1, further comprising:

first depositing a starting layer of amorphous silicon provided with an anti-crystallization dopant; and

subsequently depositing a silicon based top layer on top of the starting layer to finalize the lower amorphous silicon layer.

15. The method according to claim 14, wherein depositing the starting layer comprises using Si_nH_(2n+2) as a silicon precursor, wherein n is at least 2, at a deposition temperature below 500°

C.

16. The method according to claim 14, wherein subsequently depositing a silicon based layer on top of the starting layer is performed at a deposition temperature between 500°

C. and 550°

C.

17. The method according to claim 14, wherein the starting layer is less than 10 nm thick.

18. The method according to claim 1, wherein the anti-crystallization dopant keeps the lower silicon layer amorphous during heating the substrate to the temperature above 500°

C.

19. The method according to claim 1, further comprising:

anisotropically etching the lower amorphous silicon layer through open portions between the vertical portions of the second conformal layer;

removing the remaining portions of the second conformal layer; and

,

anisotropical etching the substrate through the open portions of the lower amorphous silicon layer thereby patterning the substrate.

21. A semiconductor device formed by a method according to claim 1 or 20.

20. A method of forming a semiconductor device, comprising:

patterning a substrate, wherein patterning the substrate comprises, in order;

forming a lower hard mask layer on the substrate;

providing a lower amorphous silicon layer above the lower hard mask layer, the lower amorphous silicon layer comprising an anti-crystallization dopant;

forming an upper hard mask layer above the lower amorphous silicon layer by a method comprising heating the substrate to a temperature above 550°

C.;

providing an upper amorphous silicon layer above the upper hard mask layer;

providing a photoresist film above the upper amorphous silicon layer;

exposing and developing the photoresist film to form a photoresist pattern;

anisotropically etching the photoresist pattern into the upper amorphous silicon layer;

depositing a first conformal layer over exposed surfaces and over the substrate;

anisotropically etching the first conformal layer to remove horizontal portions of the first conformal layer while leaving vertical portions of the first conformal layer at sidewalls of patterned features in the upper amorphous silicon layer;

removing the upper amorphous silicon layer;

anisotropically etching the upper hard mask through open portions between the vertical portions of the first conformal layer;

removing remaining portions of the first conformal layer;

anisotropically etching the lower amorphous silicon layer through open portions of the upper hard mask layer;

removing the upper hard mask layer;

depositing a second conformal layer over exposed surfaces at the surface of the substrate;

anisotropically etching the second conformal layer to remove the horizontal portions of the second conformal layer while leaving the vertical portions of the second conformal layer;

removing the lower amorphous silicon layer;

anisotropically etching the lower hard mask through open portions between the vertical portions of the second conformal layer;

removing remaining portions of the second conformal layer; and

anisotropically etching the substrate through open portions of the lower hard mask layer.