Method for packaging circuits

• US 10,453,704 B2
• Filed: 10/31/2016
• Issued: 10/22/2019
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Poo, Chia Y., Waf, Low Siu, Jeung, Boon Suan, Koon, Eng M., Kwang, Chua Swee
• Primary Examiner(s): Nguyen, Donghai D
• Application Number:
  US15/339,290
• Publication Number:
  US 20170047231A1
• Time in Patent Office: 1,086 Days
• Field of Search: 29832, 29841, 29842, 29846, 29412, 438113
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49794 : Dividing on common outline

Abstract

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Claims

1. A method, comprising:

providing a plurality of integrated circuit dice;

providing a substrate having electrical signal terminals thereon with at least two of the electrical signal terminals being interconnected;

fixing a first die on the substrate over a first group of the electrical signal terminals;

fixing a second die on the substrate over a second group of the electrical signal terminals;

forming electrical connections from first die to first group of electrical signal terminals;

forming electrical connections from second die to second group of electrical signal terminals;

removing a backside of the substrate to expose the terminals; and

separating the first and second dice from a remainder of the substrate with the first and second dice being adapted to electrically communicate through at least the interconnected electric signal terminals.

2. The method of claim 1, wherein separating the first and second dice includes filling the gap between the first die and the second die with an insulative material.

3. The method of claim 2, wherein filling the gap includes filling the gap with an encapsulant.

4. The method of claim 2, wherein filling the gap includes filling the gap with a benzocyclobutene material.

5. The method of claim 2, wherein separating the first and second die includes forming a memory module.

6. The method of claim 1, wherein the electrical connections from the first die includes forming metal traces from the first die.

7. The method of claim 1, wherein forming the electrical connections from the second die includes forming metal traces from the second die.

8. The method of claim 1, wherein providing the substrate includes providing a substrate having an integrated circuit memory device.

9. The method of claim 1, wherein providing the substrate includes providing a substrate having I/O pads on a top surface of the substrate.

10. The method of claim 1, wherein removing the backside of the substrate to expose the terminals includes backgrinding the backside of the substrate.

11. The method of claim 1, wherein removing the backside of the substrate to expose the terminals includes etching the backside of the substrate.

12. The method of claim 1, wherein removing the backside of the substrate to expose the terminals includes singulating the first and second die from a remainder of the substrate.

13. The method of claim 1, wherein forming the electrical connections from the first die to the first group of electrical signal terminals includes forming a metal trace from I/O pads on a top surface of the first die down the side of the first die to the first group of electrical signal terminals.

14. The method of claim 1, wherein forming the electrical connections from second die to the second group of electrical signal terminals includes forming a metal trace from I/O pads on a top surface of the second die down the side of the second die to the second group of electrical signal terminals.