Method of semiconductor integrated circuit fabrication
First Claim
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1. A device comprising:
- a metal layer disposed over a substrate;
a catalyst layer disposed on the metal layer, the catalyst layer having a first sidewall and an opposing second sidewall and a top surface extending from the first sidewall to the second sidewall;
a plurality of carbon nanotubes (CNTs) disposed on the catalyst layer such that the plurality of CNTs extend continuously over the top surface of the catalyst layer from the first sidewall of the catalyst layer to the opposing second sidewall of the catalyst layer;
a dielectric layer disposed adjacent to the plurality of CNTs; and
a hard mask layer disposed over the substrate, andwherein the metal layer includes a first portion and a second portion, the catalyst layer extending from the first portion of the metal layer and the hard mask layer extending from the second portion of the metal layer.
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Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
36 Citations
20 Claims
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1. A device comprising:
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a metal layer disposed over a substrate; a catalyst layer disposed on the metal layer, the catalyst layer having a first sidewall and an opposing second sidewall and a top surface extending from the first sidewall to the second sidewall; a plurality of carbon nanotubes (CNTs) disposed on the catalyst layer such that the plurality of CNTs extend continuously over the top surface of the catalyst layer from the first sidewall of the catalyst layer to the opposing second sidewall of the catalyst layer; a dielectric layer disposed adjacent to the plurality of CNTs; and a hard mask layer disposed over the substrate, and wherein the metal layer includes a first portion and a second portion, the catalyst layer extending from the first portion of the metal layer and the hard mask layer extending from the second portion of the metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a first conductive feature and second conductive feature disposed over a semiconductor substrate, the first conductive feature having a first width; a catalyst layer disposed over the first conductive feature without being disposed over the second conductive feature; a plurality of carbon nanotubes (CNTs) extending from the catalyst layer, the plurality of CNTs have the same first width as the first conductive feature; and a dielectric layer extending from the second conductive feature to at least one carbon nanotube from the plurality of CNTs. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A device comprising:
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a conductive layer disposed over a substrate, wherein the conductive layer includes a first portion and a second portion that extend to the same height over the substrate; a catalyst layer disposed on a top surface of the first portion of the conductive layer such that the catalyst layer physically contacts the top surface of the first portion of the conductive layer; a plurality of carbon nanotubes (CNTs) extending from the catalyst layer; a hard mask layer disposed on a top surface of the second portion of the conductive layer such that the hard mask layer physically contacts the top surface of the second portion of the conductive layer; and a dielectric layer extending from the hard mask layer to at least one of the CNTs. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification